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In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage ($\text{V}_{\text {th}}$) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a $\text{V}_{\text {th}}$ shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage. [ABSTRACT FROM AUTHOR]

This study investigates an abnormal degradation induced in a moist environment. Although devices maintain optimal performance under bias stress operation in a vacuum, an abnormal hump is observed in capacitance–voltage (${C}$ – ${V}$) electrical characteristics under negative bias stress (NBS) operation in a moist environment. Electrolysis of the H2O model is proposed to explain the degradation. An asymmetric stress condition, with ${V} _{\text {GD}} = {0}$ V, is designed to confirm that a vertical electric field causes the electrolysis of H2O, which is the reason for the hump phenomenon in the ${C}$ – ${V}$ curve. Moreover, COMSOL simulation and ${C}$ – ${V}$ measurement of the source and drain parasitic capacitances are utilized to clarify the precise degradation position and support the mechanism. The results from electrical measurement suggest that a vertical electric field can cause instability in a moist environment. [ABSTRACT FROM AUTHOR]

In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ($\text{I}_{\mathrm{ on}}$) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device. [ABSTRACT FROM AUTHOR]

This article presents an analytical method for parameter extraction in oxide semiconductor field-effect transistors (OS FETs), including threshold voltage (VT), effective channel length (Leff), source–drain series resistance (RSD), and intrinsic effective mobility (μint). An analytical expression of effective mobility (μeff) is implemented with the consideration of percolation conduction and RSD effects. This method relies on the concept of Y-function method and the channel length dependent measurement. The extraction results are compared to those from the combination of transfer length method (TLM). It has been shown that a better accuracy of the extracted parameters is achieved with the proposed method. Furthermore, transfer characteristics are resimulated based on the extracted parameters, in which a good match between measurement and simulation is obtained. [ABSTRACT FROM AUTHOR]

This work studies the effect of the location of the light shielding (LS) layer on negative bias illumination stress (NBIS) instability in self-aligned top-gate amorphous indium-gallium-zinc oxide thin-film transistors (SA-TG a-InGaZnO TFTs). Although the NBIS instability can be mitigated by introducing a fully covered LS layer, it causes an unwanted parasitic capacitance, as evidenced by capacitance–voltage (C – V) measurements. An alternative solution, in which the device that is partially covered by the LS layer at the source side, is proposed to optimize the tradeoff. This study suggests that an LS layer could be adopted in the SA-TG configuration, as it is versatile in different structural designs, depending on the requirement of targeted applications. [ABSTRACT FROM AUTHOR]

An ultrawideband absorptive common-mode filter (A-CMF) with a newly developed defected ground structure (DGS) is proposed in this article. The DGS miniaturized to a subwavelength size is able to totally suppress the common-mode noise while maintaining the signal integrity of the differential mode. In addition, the reflection and radiation of the common-mode noise are negligible in the stopband. For quick design, a simplified equivalent circuit model is also proposed. This model can be employed to estimate the resistances of the lumped resistors embedded in the DGS to obtain a very wide absorption band. In the demonstrated example, the fractional bandwidth determined by a 90% absorption efficiency can achieve as large as 104% around 3.55 GHz for an A-CMF realized on a simple two-layer printed circuit board. Such a widely absorptive bandwidth is never achieved before to our knowledge. The design methodology is validated by full-wave simulation. Finally, real measurement of the design is also carried out to confirm the design and analysis. [ABSTRACT FROM AUTHOR]

In this work, degradation due to carrier injection at the etch-stop layer was observed under dynamic switching. A significant threshold voltage shift is observed in alternating current stress but is absent in direct current stress. A model which transitions from the accumulation to depletion phases indicates electron-trapping at the etch-stop layer since the transition time is insufficient for carriers to drift back to the source/drain electrodes. Results are discussed through both horizontal and lateral band diagrams to confirm back channel injections. Also, comparing transfer curves with capacitance-voltage curves at the same threshold voltage in different structure devices provides direct evidence of electron-trapping regions. Finally, COMSOL simulation is performed to confirm the difference in electron-trapping between back channel and corner regions, a difference which leads to an abnormal hump during capacitance-voltage measurements. [ABSTRACT FROM AUTHOR]

Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI. [ABSTRACT FROM AUTHOR]

In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control. [ABSTRACT FROM AUTHOR]

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field. [ABSTRACT FROM AUTHOR]

This study investigates short channel (length $< 20~\mu \text{m}$) p-type organic thin-film transistor (OTFT) devices which exhibit off-state leakage in their ID–VG characteristics. This phenomenon is attributed to the fact that when a lower positive gate voltage is applied, gate voltage cannot control the back channel, causing back channel leakage. The behavior of back channel leakage is confirmed by the OTFT saturated-regime drain-current formula multiplied by channel length. For dual gate OTFT devices, a top gate voltage sweep and fixed different bottom gate voltages are applied, which indicates that the conduction path is distributed throughout the entire organic semiconductor (OSC) layer, and the back channel leakage can be suppressed by a positive bottom gate voltage. Finally, using dual gate sweeping for a dual gate OTFT device allows the top and bottom gate voltage to simultaneously control the front and back channels, causing a suppression of the back channel leakage, an improvement in subthreshold swing (SS) from 420 to 200 (mV/decade) and an on current increase from $\textsf {7.8}\times \textsf {10}^{-\textsf {8}}$ to $\textsf {3.3}\times \textsf {10}^{-\textsf {7}}$ A at VG-Vsub-threshold = −8 V for the W/L $=50/20~\mu \text{m}$ device. [ABSTRACT FROM AUTHOR]

This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance. [ABSTRACT FROM AUTHOR]

We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) enhancement is due to the reduction of effective length, and the OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage (${V}_{\text {th}}$) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down. [ABSTRACT FROM AUTHOR]

This letter investigates variations in polycrystalline silicon thin film transistor (TFT) performance under illumination and negative bias temperature instability (NBTI) tests due to different dehydrogenation annealing temperatures during the fabrication process. The depth of the density of state (DOS) in polysilicon can be indirectly determined by the TFT response to light illumination, since dangling bonds act as recombination centers. The electrical characteristics of TFTs after undergoing NBTI can also be indicative of the bonding type of silicon atoms. By analyzing the results of these reliability tests, the type of DOS can be clarified, which is beneficial for realizing the relationship between performance and reliability. [ABSTRACT FROM AUTHOR]

High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies. [ABSTRACT FROM AUTHOR]

In order to better understand the reliability issues in top-gate a-InGaZnO (a-IGZO) thin-film transistors, this letter investigates the degradation mechanism of a device under self-heating stress (SHS). After applying hot carrier stress, a negative threshold voltage (${V} _{\text {TH}}$) shift, a hump effect, and normally- ON current degradation were found. COMSOL simulation results of hydrogen diffusion in the source and drain (n+ region) of a-IGZO show that Joule heat was generated in the channel during SHS, which leads to hydrogen diffusion in the central and side channels. The unequal channel thermal effect results in a hump effect in the electrical characteristics, and the self-heating effect becomes more prominent as the channel width increases. To minimize the effects of these abnormal phenomena under high current operation in future display applications, a method of creating structural divisions in the channel width is used to aid overall heat dissipation and reduce the effect of SHS degradation. [ABSTRACT FROM AUTHOR]

In this letter, we integrated a floating bottom gate (BG) as a light shielding layer in a thin-film transistor (TFT). We observed abnormal ${I}_{D}$ – ${V}_{D}$ output characteristics and unsaturated current characteristics. In addition, drain-induced barrier lowering has a significant impact on ${I}_{D}$ – ${V}_{D}$ characteristics as the drain voltage increases. These phenomena are due to changes in electrical potential that occur due to the capacitive coupling effect. Technology computer aided design simulations explained and correlated well with our observations. Then, a physical model is proposed to verify the abnormal electrical characteristics. Grounding the BG light shield was found to provide better control over the threshold voltage and total current performance. This letter results may lead to better applications in the TFT driving circuits. [ABSTRACT FROM AUTHOR]

This paper demonstrates the cumulative effects of compressive stress and high current stress at high temperature in flexible a-InGaZnO4 thin-film transistors. An abnormal hump can be found in the subthreshold regime in the results from a reliability test that combines high temperature and high current stress with mechanical bending at 10 mm. During this stress, holes will tend to inject into the defects in the etching stop layer near the source side, which is induced by compressive bending. A COMSOL simulation was performed and confirmed that defect generation occurs in the etching stop layer during compressive bending. Further, the path of the back-channel leakage current caused by the localized trapped holes was also confirmed by changing the width/length of thin film transistors (TFTs) in the reliability test. The precise hole trapping distribution was verified by a single side capacitance-voltage measurement and source/drain interchange measurement. [ABSTRACT FROM AUTHOR]

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper. [ABSTRACT FROM AUTHOR]

This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage. [ABSTRACT FROM AUTHOR]

This paper systematically studies high-current-induced effects, hot-carrier effects, and self-heating effects in flexible low-temperature polycrystalline-silicon thin-film transistors fabricated on polyimide. By utilizing I – V and various-frequency C – V measurements, the exact location of defects generated by the self-heating effects can be clarified. The degradation mechanism is found to originate from asymmetric negative-bias temperature instability. After clarifying this mechanism, the self-heating effects were shown to be alleviated by manipulating the fabrication of the buffer layer, thereby improving heat dissipation capabilities. [ABSTRACT FROM PUBLISHER]

This letter analyzes performance and reliability of inverted staggered type amorphous indium–gallium–zinc oxide devices in a moist environment with H2O molecules in the passivation layer. There is a negative threshold voltage shift ( \vartriangle ~\textV\mathrm {{th}} ) in the saturation region (VD = 10 V), which increases with decreasing channel length. We propose that this is explained by the drain-induced barrier lowering that is due to the H2O molecules. Moreover, a hydrogen bonding model under bias stress is also proposed, in contrast to the conventional H2O doping model. Recovery behavior after bias stress and ac operation were utilized to distinguish the difference between these models. [ABSTRACT FROM PUBLISHER]

UV‐sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV‐sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV‐light‐sensing properties of an amorphous InGaZnO4 (IGZO) thin‐film transistor with a dual‐gate structure and relatively small device size (width/length = 50 µm/10 µm) that achieves high sensitivity through a threshold‐voltage‐(Vth)‐adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 106. Furthermore, the UV sensitivity of the dual‐gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual‐gate a‐IGZO transistor to be used for high‐performance UV sensing while being effectively integrated in display applications. [ABSTRACT FROM AUTHOR]