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This letter proposes a loop-free autocalibration technique for self-balancing of flying capacitors in a three-level dc–dc buck converter. The proposed converter utilizes a dual-path power stage with balancing switches that adaptively short flying capacitors at de-energizing phases. Thus, the dual-path three-level converter ensures that flying capacitor voltages are self-balanced at half the input voltage without using additional feedback calibration loops, leading to robust operation and competitive efficiencies. The prototype was fabricated in the 0.13- μ m CMOS BCD process and adopted two flying capacitors of 4.7 μ F each and an inductor of 10 μ H with a dc resistance of 128 mΩ. When an 8-V input was converted to a 3-V output voltage with a load current of 400 mA, the measured efficiency was 88.6% at 800 kHz switching while flying capacitors are automatically balanced.

A DC-DC converter, which tracks minimum power loss under various conditions, is presented in this paper. With this DC-DC converter, a new approach for optimum efficiency, which implements theoretical equations intactly at the circuit level, was adopted. This approach has high reliability against process variation. The concept of lossless soft-switching was also adopted in discontinuous-conduction-mode (DCM) operation. The proposed DC-DC converter has a maximum power efficiency of 91% at the switching frequency of 1 MHz. The proposed converter is able to maintain a maximum power efficiency of around 90% over the whole range of input voltage from 2.9 to 4.5 V and output voltage from $-$ 3.8 to $-$ 5.9 V. This chip is implemented in a 0.35 $\mu$ m BCD process and occupies an area of 2.1 $\times $ 1.4 mm $ ^{2}$ .

This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components ( 1 pF and 80 kΩ in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm2 of core area (w/o power transistors) using 0.18 μm I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.

While the demand for micro-energy harvesters (μEHs) is increasing (for seamless energy source in applications such as wireless sensor node), two major problems still obstruct versatile use of them. The first problem is the self-startup capability. Because many wireless sensor nodes are likely to be located where human-maintenance is difficult, starting them up manually can be as difficult as replacing the battery. Its realization has been difficult because μEHs must be able to turn itself on without any stored energy. Some previous works have reported such a function: some needed high voltage [1] or vibration [2] and one used a transformer as a starter [3]. The other problem is the maximum power point tracking (MPPT) capability. Because it is known that MPPT algorithms usually require considerable power consumption [4], using them in μEHs is impractical. This paper suggests a new boost converter architecture and MPPT control method which can bring μEH into practical use.