Search

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F2. Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

Negative-differential transconductance characteristics at room temperature with a peak-to-valley ratio of about two were observed in 30-nm square-channel silicon-on-insulator nMOSFETs with degenerately doped bodies. High channel-doping concentration creates the degeneracy in the p-type body of the self-aligned SOI MOSFET and consequently, enables band-to-band tunneling between degenerate body and source-drain. I/sub DS/-V/sub DS/ curves in the negative drain bias region also show band-to-band tunneling current as in the case of forward-biased p-n tunnel junctions.

We have developed a patterning technique to define ultrafine lines with high density and good uniformity using sidewall structures. Approximately 50 nm multiple lines, which have 70 nm as the narrowest space between the lines, are defined by the pattern multiplication technique. Linewidths are measured at several points on wafers and their uniformity is verified. These patterns have a good uniformity (deviation 2.26–4.35 nm). Also, die-to-die uniformity is very good. The advantage of this technique is the easy control (using sidewall width control) of the line and space of patterns. This technique is free from the proximity effect because of the process using a sidewall hard mask. Thus, it is expected that the pattern multiplication technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.

Basic operation of a dynamic exclusive-OR gate implemented by a field effect transistor and a single-electron transistor is experimentally demonstrated, for the first time. Logic output voltage shows full swing operation at a supply voltage of 20 mV. Fabricated single-electron transistors are advantageous for implementing a multi-gate single-electron logic circuit.

For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) field effect transistor with the depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guarantee the compatibility with complementary MOS process technology. Moreover, critical dimension depends...