Search

Your search keyword '"Ming-Jer Kao"' showing total 49 results

Search Constraints

Start Over You searched for: Author "Ming-Jer Kao" Remove constraint Author: "Ming-Jer Kao" Search Limiters Peer Reviewed Remove constraint Search Limiters: Peer Reviewed
49 results on '"Ming-Jer Kao"'

Search Results

1. Effects of Nonlinearity on Velocity, Acceleration and Pressure Gradient in Free-Stream Zone of Solitary Wave over Horizontal Bed—An Experimental Study

2. Particle acceleration and pressure gradient in a solitary wave traveling over a horizontal bed

3. 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

4. Hydrodynamic Features of an Undular Bore Traveling on a 1:20 Sloping Beach

5. Evolution of Velocity Field and Vortex Structure during Run-Down of Solitary Wave over Very Steep Beach

6. Application of SIM, HSPIV, BTM, and BIV Techniques for Evaluations of a Two-Phase Air–Water Chute Aerator Flow

7. A 6-[F.sup.2] bit cell division based on one transistor and two uneven magnetic tunnel junctions structured and low power design for MRAM

8. On the improvement of gate voltage swings in delta-doped GaAs/In(x)Ga(1-x)As/GaAs pseudomorphic heterostructures

9. Brief rapid thermal treatment effect on patterned CoFeB-based magnetic tunneling junctions

10. Interfacial and annealing effects on magnetic properties of CoFeB thin films

11. The switching behaviors of submicron magnetic tunnel junctions with synthetic antiferromagnetic free layers

12. Velocity Fields in Near-Bottom and Boundary Layer Flows in Prebreaking Zone of a Solitary Wave Propagating over a 1:10 Slope.

27. Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration.

28. Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV).

29. Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration.

30. An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration.

31. Write Disturbance Modeling and Testing for MRAM.

32. A 6-F2 Bit Cell Design Based on One Transistor and Two Uneven Magnetic Tunnel Junctions Structure and Low Power Design for MRAM.

33. Reduction in critical current density for spin torque transfer switching with composite free layer.

34. Enhanced Thermal Efficiency in Phase-Change Memory Cell by Double GST Thermally Confined Structure.

35. Improvement of Transport Properties in Magnetic Tunneling' Junctions by Capping Materials.

36. Improvement switching characteristics of toggle magnetic random access memory with dual polarity write pulse scheme.

37. Improvement of Switching Field in Magnetic Tunneling Junction Using Ru/Ta Capping Layer.

38. Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme.

40. Key enabling technologies of 300mm 3DIC process integration.

49. Fast-Write Resistive RAM (RRAM) for Embedded Applications.

Catalog

Books, media, physical & digital resources