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A new metal-ferroelectric-metal (MFM) capacitor based memory scheme is proposed and designed for which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, SL flags during the period of power-on. A ferroelectric random access memory embedded radio-frequency identification (RFID) tag chip is prepared with an industry-standard complementary metal-oxide-semiconductor (MOS) process.

The proposed UHF Gen2 RFID chip expands its applications to both FFC and NFC through dual field communication scheme with the dual antenna ports. An RF front end circuit with dual field communication antenna ports and the embedded FeRAM technology on the passive UHF Gen2 RFID chip enables the excellent operating performances and the low cost chip for the tag chip applications from the item level to pallet. The metal-ferroelectric-metal (MFM) capacitor, which is the replacement capacitor device for metal-insulator-metal (MIM) or poly-insulator-poly (PIP), is composed of the ferroelectric material as a dielectric insulator. The MFM capacitor is made simultaneously during the FeRAM memory cell process integration without any additional process integration cost. The MFM capacitor of PZT with the thickness of 0.15μm has the high capacitance value of 20-40 fF at unit μm2 area size. The MFM can be stacked over the CMOS layout area, which saves dramatically the capacitor layout area. The MFM capacitor also has the high breakdown voltage at the thickness of 0.15 μm, which enhances the reliability in the surging electrostatic discharge (ESD) current into the dual antenna ports. The pumping capacitors of the multi-stage voltage pump are composed of the multiple MFM capacitors of the capacitance value of the element device of 1-2 pF. The reservoir capacitors of the VDD power line also are composed of the MFM capacitors with the total capacitance value of 500-1000 pF. The rectification diode device is composed of the near zero threshold voltage NMOS (ZNMOS) transistor with a threshold voltage level of 0.1-0.2 V. [ABSTRACT FROM AUTHOR]

In this paper, high performance read-out integrated circuits (ROIC) for infrared (IR) image sensor applications is proposed. Because an uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems process, the resistance of bolometer by each process does not appear same value under same temperature condition. This resistance variation generates a different output signal for same input by each chip. In order to improve on these drawbacks, a ROIC, which compensates for the error described above, was designed. Instead of a single input mode, a differential input mode ROIC was proposed and thus, a new circuit structure was proposed. Using results from a computer simulation, improvements such as that the effect of the process error was decreased 10–12% without an additional compensation circuit was found. Based on the simulation results, a prototype device including a ROIC and a micro bolometer with 16 × 16 cell arrays was fabricated and characterized. [ABSTRACT FROM AUTHOR]

The maximum peak-to-peak radio frequency (RF) signal antenna voltage level can be extended to reach to over 12 Vpp, -6 V to +6 V. Thus it is desirable that the electro-static discharge (ESD) device does not turn on at the normal operating RF antenna signal voltage level. The turn-on threshold negative voltage of the ESD device of the PN diode type is around -0.5 V in the conventional radio frequency identification (RFID) chip. The asymmetric threshold voltage characteristics of the ESD device of the RFID chip makes the distortion of the RF antenna signal at the high intensity RF input field. In the proposed floating base vertical PNP ESD device, N-type doped N-WELL floating base is sandwiched between two p-type P+ emitter and P-WELL collector. Floating base BJT ESD device enhances the performance of parasitic BJT current in the ESD mode. During the negative voltage phase of RF antenna input signal, the negative voltage of RF antenna input is extended to around -10 V. This extension of RF antenna input operation voltage range makes to prevent from any distortion of RF antenna signal at the high RF input field. The measured HBM ESD protection level of the floating base BJT ESD device is over 2000 V with the P+ anode layout area of 400 μm2. [ABSTRACT FROM AUTHOR]

N-WELL floating base is sandwiched between P+ emitter and P-WELL collector in the proposed floating base vertical PNP electro-static discharge (ESD) protection device. Floating base bipolar junction transistor (BJT) ESD protection device increases the current performance of the parasitic BJT in the ESD mode. During the negative voltage phase of RF antenna signal, the negative voltage range of RF antenna signal is extended to around -10 V at the high RF power field without latch-up failure. The minimum P+ anode layout area of the floating base type BJT ESD device is 400 μm2 for the target ESD voltage of 2000 V in human body model (HBM) mode. The parasitic capacitance of the floating base type BJT ESD protection device is about 0.4 pF. The layout area of the proposed floating base type BJT ESD protection device is 50% smaller that of the conventional NMOS diode type ESD protection device for the target ESD voltage of 2000 V in HBM mode. The rewards of the floating base type BJT ESD device will come in the form of improved yields, higher reliability, and substantially lower costs of RFID chip manufacturing. [ABSTRACT FROM AUTHOR]

The metal-ferroelectric-metal (MFM) capacitor in ferroelectric random access memory (FeRAM) security embedded RFID chip is used not only in the memory cell region but also used in the analog and digital circuit area for low cost capacitance device and high security algorithm. MFM based security FeRAM braces for a wide range of security threats such as reverse engineering, cloning, and tampering. High security performance solution of on-chip FeRAM based register key is implemented to prepare against security attacking. RF transferring sensitivity properties with MFM capacitor are almost same or better than that with poly-insulator-poly (PIP) capacitor and metal-insulator-metal (MIM), and MOS capacitor. The measured power consumption of FeRAM embedded RFID chip without crypto processor engine is about 10μ W with the write sensitivity of -18dBm. [ABSTRACT FROM AUTHOR]

For a longer working distance between passive tags and the reader, the ferroelectric based technologies are proposed in UHF (860-960 MHz) band transponder. The small ferroelectric capacitor layout area with a stacked capacitor structure over circuit region and a large dielectric permittivity of 250 to 500 and small 1T1C cell array layout area with simple 2T2C based reference scheme allow small chip size. The low operation voltage of 1.5 V to 2.0 V without high voltage boosting scheme also contribute to small power consumption and low cost. [ABSTRACT FROM AUTHOR]

The reliability of imprint patterns molded by stamps for industrial application of nanoimprint lithography (NIL) is an important issue. Usually, defects can be produced by incomplete filling of negative patterns and the shrinkage phenomenon of polymers in conventional NIL. In this paper, the patterns that undergo a varied temperature or varied pressure period during the thermal NIL process have been investigated, with the goal of resolving the shrinkage and defective filling problems of polymers. This paper also studies the effects on the formation of polymer patterns in several profiles of imprint processes. Consequently, it is observed that more precise patterns are formed by varied temperature (VT-NIL) and varied pressure (VP-NIL). The NIL (VT-NIL and VP-NIL) process has a free space compensation effect on the polymers in stamp cavities. From the results of the experiments, the polymer's filling capability can be improved. VT-NIL is merged with the VP-NIL, resulting in a better filling property. The patterns that have been imprinted in merged NIL are compared with the results of conventional NIL. This study achieves improvement in the reliability of the results of thermal NIL. [ABSTRACT FROM AUTHOR]

The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub block sections. The sub block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub block intervals. When one of four sub blocks is activated, the two MSLs located at the edge of four sub blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is a bout less than 50 mV. The average sensing voltage with 2Pr value of 5 µC/cm² and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 µC/cm². [ABSTRACT FROM AUTHOR]

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5μm CMOS technology with 5 V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which the advantages of both PFDs can be combined. The sequential PFD has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by operating the appropriate PFD connected to the well-adjusted charge pump and regulating the ratio of loop bandwidth to input frequency during the acquisition process, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. This structure can improve the trade-off between acquisition behaviour and locked behaviour. The proposed PLL structure is designed to use 1.5 µm CMOS technology with 5 V supply voltage. [ABSTRACT FROM AUTHOR]

Abstract-The trench insulated gate bipolar transistor (TIGBT) suffers from breakdown voltage degradation due to the electric field crowding at the corner of the trench gate in the forward blocking state. We propose a new TIGBT structure that has a deep p+ layer beneath the trench emitter to distribute the concentrated electric field. The deep p+ layer of the structure is formed by ion implantation at the bottom of the trench after a partial etching of the p-base region. The proposed structure improves the breakdown voltage compared to conventional TIGBTs without changing the threshold voltage and with quite a small change of ON-state voltage drop. The distribution of the electric field is also changed by its design parameters. When the positions of the trench gate corner and the deep p+ layer are nearer, the breakdown voltage is higher. The distribution effect operates when the doping level of the deep p+ layer exceeds the appropriate value to prevent punchthrough between the metal electrode and the n-drift region. This structure can be applied easily to various TIGBTs with simple-process additions. [ABSTRACT FROM AUTHOR]

Highly efficient and bright organic light-emitting diodes have been realized by inserting a thin insulating lithium fluoride (LiF) layer in the tris-(8-hydroxyquinoline) aluminum (Alq3) with conventional organic layers. By comparing the performances of newly devised devices as a function of the position of the LiF in the Alq3 layer, the authors propose the optimal position of the LiF in the Alq3 layer. Experimental results show that the efficiency and brightness of the newly devised device with LiF in the Alq3 layer were seven times higher than that without LiF in the Alq3 layer. [ABSTRACT FROM AUTHOR]

ZnO nanowires were grown between two Au electrodes on an Al2O3-deposited Si wafer. Photoresponse, photoresponse spectrum, and current–voltage (I–V) studies were performed for the investigation into photoconduction mechanism in these nanowires. The photoresponse of the nanowires under the continuous illumination of light with above- or below-gap energies was slow, which indicates that photocurrent in the nanowires is surface-related rather than bulk-related. The photoresponse spectrum represents the above- and below-gap absorption bands for the photocurrents. The I–V characteristics under the illumination of the above-gap light are ohmic, but the characteristics under the illumination of the below-gap light are Schottky. This observation indicates that the above-gap light lowers the potential barrier built in the contact between the ZnO nanowires and electrodes, but that the below-gap light does not lower the potential barrier. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) dynamic random-access memory (DRAM) with TSVs has been proposed due to continuous demands for low-power and high-density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self-calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double-data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V. [ABSTRACT FROM AUTHOR]