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In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

The behavior of FinFET devices is analyzed under electrostatic discharge (ESD) conditions for various layout and process conditions. The results have shown that the possible extreme sensitivity of FinFET devices might not be a showstopper for the advanced nanotechnologies if ESD is considered during the technology development.

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveal an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the key advantages over bulk MOSFETs including reduced leakage, excellent subthreshold slope, and a better voltage gain without degradation of noise or linearity.

Research involving the influence of gate-source-drain architecture on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors is described and discussed.

In this study, the radiation effects of electron beam (e‐beam) on field‐effect transistors (FETs) using transition‐metal dichalcogenides (TMD) as a channel are carefully investigated. Electron‐hole pairs (EHPs) in SiO2 generated by e‐beam irradiation induce additional traps, which change the surface potential of the TMD channel, resulting in strong negative shifts of transfer characteristics. These negative shifts, which remind one of n‐doping effects, are highly affected not only by the condition of e‐beam irradiation, but also by the gate bias condition during irradiating. As a result of the e‐beam irradiation effect, band bending and contact resistance are affected, and the degree of formation of oxide traps and interface traps varies depending on the gate bias conditions. In the case of VG > 0 V application during e‐beam irradiation, the negative shifts in the transfer characteristics are fully recovered after ambient exposure. However, the interface traps increase significantly, resulting in variations of low‐frequency (LF) noise and time‐dependent current fluctuations. [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

Total-ionizing-dose effects are evaluated in vertical-charge-trapping NAND devices with silicon oxynitride (SiON) and SiO2 tunneling layers. Processing splits include SiON tunneling layers with and without H2/D2 high-pressure annealing. Programmed devices were irradiated to 500 krad(SiO2) with 10-keV X-rays and annealed for 30 min. Second programming after annealing does not fully restore the original, programmed state. Radiation-induced trapped holes compensate for deeply trapped electrons that are injected into the dielectric during device programming. Throughout the full irradiation and annealing sequence, threshold voltages remain large enough to enable successful nonvolatile (NV) memory application. [ABSTRACT FROM AUTHOR]

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

Charge trapping is arguably the most important detrimental mechanism distorting the ideal characteristics of MOS transistors, and nonradiative multiphonon (NMP) models have been demonstrated to provide a very accurate description. For the calculation of the NMP rates at room temperature or above, simple semiclassical approximations have been successfully used to describe this intricate mechanism. However, for the computation of charge transition rates at cryogenic temperatures, it is necessary to use the full quantum mechanical description based on Fermi’s golden rule. Since this is computationally expensive and often not feasible, we discuss an efficient method based on the Wentzel–Kramers–Brillouin (WKB) approximation in combination with the saddle point method and benchmark this approximation against the full model. We show that the approximation delivers excellent results and can, hence, be used to model charge trapping behavior at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high- ${k}$ CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO2 and HfO2 layer. We show that NBTI is dominated by defects in the SiO2 layer, whereas PBTI arises mainly from defects in the HfO2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site. [ABSTRACT FROM AUTHOR]

Perpendicular Magnetic Anisotropy (PMA) is a key requirement for state of the art Magnetic Random Access Memories (MRAM). Currently, PMA has been widely reported in standard Magnetic Tunnel Junction material stacks using MgO as a dielectric. In this contribution, we present the first report of PMA at the interface with a high-j dielectric grown by Atomic Layer Deposition, HfO2. The PMA appears after annealing a HfO2\Co\Pt\Ru stack in N2 with the Keff of 0.25 mJ/m² as determined by Vibrating Sample Magnetometry. X-Ray Diffraction and Transmission Electron Microscopy show that the appearance of PMA coincides with interdiffusion and the epitaxial ordering of the Co\Pt bilayer. High-κ dielectrics are especially interesting for Voltage Control of Magnetic Anisotropy applications and are of potential interest for low-power MRAM and spintronics technologies. [ABSTRACT FROM AUTHOR]

Field‐effect transistors (FETs), using transition metal dichalcogenides (TMD) as channels, have various types of interfaces, and their characteristics are sensitively changed in temperature and electrical stress. In this article, the effect of fast cyclic thermal stress on the performance of FETs using TMD as a channel is investigated and introduced. The Al2O3 passivation layer is deposited onto the TMD channel by atomic layer deposition process, and the hysteresis decreases and the direction changes from clockwise to counterclockwise. Applying cyclic thermal stress that rapidly heats and cools by 90 K in a 20 s cycle increases and decreases drain current repeatedly as charges move between the TMD channel and the interface traps. As cyclic thermal stress is applied, permanent interfacial damage occurs, resulting in increased interface trap density at the bottom and decreased hysteresis. These experimental results are also shown through technology computer‐aided design simulations. In addition, series resistance and mobility attenuation factor increase due to the concentration of the conduction paths at the bottom of the channel. [ABSTRACT FROM AUTHOR]

A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I – V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I – V modeling results: an universal mobility degradation normalization parameter Nit,ref = ~ 4.1 × 1011/cm2 is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I – V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress. [ABSTRACT FROM AUTHOR]

Peak transient currents due to pulsed-laser or heavy-ion irradiation of Ge $p$ MOS FinFETs are nearly independent of gate bias. This is because the prompt photocurrent is due primarily to a transient source–drain shunt. In contrast, long-term diffusion charge collection is strongly gate-bias dependent. This bias dependence results from hole injection from the source in response to the transient increase in electron concentration in the channel. The transients measured at the source terminal change polarity when the strike location moves from the source to the drain, but this effect does not occur for the transients measured at the drain terminal. Charge collection mechanisms are studied using TCAD simulations. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

Pulsed-laser-induced single-event current measurements on two geometries of waveguide-integrated germanium photodiodes were conducted over a range of operating voltages to examine the impact of photodiode geometry on the transient response. Vertical p-i-n photodiodes exhibit transients with a duration that is relatively independent of the operating voltage, while the transient duration in lateral p-i-n photodiodes depends on the operating voltage. Furthermore, the experimental measurements facilitate identification of device dimensions that impact the transient response. These results can be used to identify potential radiation mitigation strategies for photodiodes operating in a radiation environment. Understanding the implications of design choices is critical for designing integrated photonic systems that balance system performance with tolerance for radiation degradation. [ABSTRACT FROM AUTHOR]

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices. [ABSTRACT FROM AUTHOR]

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (VBG) is applied only during ON-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox). Therefore, supplying an FBB during ON-state can be used to adjust device performance—as VBG modulates the channel current through Vth and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG – Vth (VBG) is kept constant under different VBG’s], the BTI reliability can be improved under FBB (due to a reduced Eox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage Vth shifts and subthreshold stretchout (SS), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and Id – Vgs measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of Vth and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep. [ABSTRACT FROM AUTHOR]

In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in 30-nm gate-length bulk and silicon-on-insulator (SOI) FinFETs for devices with fin widths of 10–40 nm. Minimal threshold voltage shifts are observed at 2 Mrad(SiO2), but large increases in low-frequency noise are found, and significant changes in defect-energy distributions are inferred. Radiation-induced leakage current is enhanced for narrow- and short-channel bulk FinFETs. Short-channel SOI FinFETs show enhanced degradation compared with longer-channel devices. Narrow- and short-channel SOI devices exhibit high radiation tolerance. Significant random telegraph noise (RTN) is observed in smaller devices due to prominent individual defects. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO2/Al2O3 gate-stack. Transistors are irradiated up to 500 krad(SiO2) and annealed at high temperatures. Irradiated devices show negative threshold-voltage Vth shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor Vth shifts are due primarily to hole trapping at oxygen vacancies in HfO2, and the increased noise is due primarily to O vacancies in Al2O3. Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures. [ABSTRACT FROM AUTHOR]

Pulsed, laser-induced, single-event current measurements on silicon-on-insulator (SOI) FinFETs at subbandgap wavelength (1260 nm) are affected by the polarization of the laser light used in the experimental testing setup. Such polarization dependence is not observed during pulsed laser, single-event effects testing on large-area silicon diodes, suggesting that polarization dependence arises due to the presence of the nanoscale fin. Plasmonic enhancement is proposed as a likely mechanism for the polarization effects due to the metal/dielectric interfaces in the fin region. The observed polarization dependence has ramifications for collection and interpretation of data acquired by pulsed laser testing. Device orientation of FinFETs and other nanoscale devices during pulsed laser testing should be considered in order to ensure consistent testing conditions and reproducible measurement results across multiple measurement campaigns. [ABSTRACT FROM AUTHOR]

We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration ${N} _{\text {it}}$. These deterministic densities ${N} _{\text {it}}$ for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible. [ABSTRACT FROM AUTHOR]

This paper presents a physically unclonable function (PUF) based on the randomness of soft gate oxide breakdown (BD) locations in MOSFETs, namely, soft-BD PUF. The proposed PUF circuit features a self-limiting mechanism that generates exactly one soft-BD spot in a pair of NMOS transistors. Highly stable “0” and “1” bits with an equal probability of 0.5 are extracted based on the locations of the generated BDs. A differential readout scheme is employed based on the proposed reference-free sense amplifier (SA), resulting in good current sensitivity and side-channel attack resilience. The soft-BD PUF, fabricated in a 40-nm CMOS process, comprises all essential periphery circuits. Measurements show that the soft-BD PUF has good data stability in a wide operating range. The native bit error rate is 0% for $V_{\text {DD}}=1\,\,\text {V}$ and above, shown by measuring 10k readout cycles among 10k PUF cells. Data stability degrades at lower supply voltage and higher temperature due to the conductivity of PUF cells and the offset of SAs. Under the nominal $V_{\textrm {DD}}$ of 0.9 V in this technology, the throughput is shown to be at least 40 Mb/s and the PUF readout consumes only 51.8 fJ/bit. The averaged hamming weight and hamming distance are 0.497 and 0.496, respectively, showing a good randomness and uniqueness. The resulting PUF data show good statistical properties by passing all the relevant tests in the NIST 800-22 suite. [ABSTRACT FROM AUTHOR]

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential. [ABSTRACT FROM AUTHOR]

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required. [ABSTRACT FROM AUTHOR]

Junction-less FETs are used as top-tier devices in a 3-D sequential integration. Due to the low thermal budget allowed in the 3-D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, a junction-less FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We observe that the reliability of junction-less FETs can be further improved by increasing the channel doping and/or the channel thickness. Correspondingly, a tradeoff exists between performance (subthreshold slope, carrier mobility), reliability, and variability. This tradeoff is verified in both planar/FinFET structures and can serve as a device optimization matrix. Furthermore, we use the non-radiative multi-phonon (NMP) theory, as implemented in the imec/T.U. Vienna BTI simulation framework “Comphy,” to investigate the degradation kinetics and show that the stress/recovery traces measured in inversion mode and junction-less nFETs can be reproduced with the same set of oxide defect parameters. This observation confirms that the reliability improvement in junction-less devices is inherent to their specific operation mode and not related to the different fabrication flows compared to standard inversion mode devices. Based on the calibrated Comphy model, we perform BTI lifetime projections, exposing for junction-less devices a substantial deviation from the commonly used power-law voltage acceleration. [ABSTRACT FROM AUTHOR]

We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current (${J}$ – ${V}$), capacitance (${C}$ – ${V}$), and conductance (${G}$ – ${V}$) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce ${J}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal–insulator–metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data is understood, and the atomic structure of the relevant stack defects is identified. [ABSTRACT FROM AUTHOR]

For sub-5 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have an impact on the transient performance of an electrostatic discharge protection diode. The 100 ns transmission line pulse (TLP) and 2 ns very fast TLP measurement results and TCAD simulations prove that the performance in bulk GAA NW-based diodes is maintained in comparison to bulk FinFET diodes. [ABSTRACT FROM AUTHOR]

The pulsed-laser single-event transient response of InGaAs FinFETs on bulk silicon substrates is investigated. Charge collection due to a source–drain shunt effect and drain-to-substrate junction charge collection contribute to the observed transients. The transient response of these silicon substrate devices is compared to that of InGaAs FinFETs on semi-insulating substrates. Faster transients with reduced peak currents and peak widths are observed on the silicon substrate devices. Simulations show hole collection by the silicon substrate. This reduces the amount of source-barrier lowering and bipolar-amplification relative to other III–V devices. Moreover, the reduced hole lifetime in the GaAs buffer layer also contributes to the relative reduction of the bipolar amplification in these devices. [ABSTRACT FROM AUTHOR]

Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]

STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent studies show that a significant error is made using the conventional methods for Δ extraction. We investigate the origin of the low accuracy. To reduce the error down to 5%, 1000 cycles or multiple ramp rates are necessary. Furthermore, the thermal stabilities extracted from current switching and magnetic field switching appear to be uncorrelated and this cannot be explained by a macrospin model. Measurements at different temperatures show that self-heating together with a domain wall model can explain these uncorrelated Δ. Characterizing self-heating properties is therefore crucial to correctly determine the thermal stability. [ABSTRACT FROM AUTHOR]

Increased sensitivity of FinFET technology to single-event latch-up (SEL) was found during 64-MeV proton beam accelerated testing and confirmed with neutron beam experiments. TCAD simulations demonstrate that the $3\times $ shallower trench isolation in FinFET technology significantly increases both \beta _{\mathrm {npn}}\cdot \beta _{\mathrm {pnp}} -product gain of parasitic CMOS SCR and SEL sensitivity. It is expected that other FinFET technologies with similar shallower trench isolation parameters will also experience increased SEL sensitivity. [ABSTRACT FROM PUBLISHER]

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist. [ABSTRACT FROM PUBLISHER]

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process. [ABSTRACT FROM PUBLISHER]

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the single defect discharge events in Ge-source n-type vertical nanowire tunnel field effect transistors, by monitoring the relaxation phase which follows bias temperature instability (BTI) stress. Threshold voltage shift induced by single discharge events follows a bimodal Weibull distribution, with the location parameter of the second mode being significantly higher than the first one. Both modes are temperature independent. Based on TCAD simulations, we propose that the second mode is associated with defects located at the source/channel junction close to the channel/oxide interface, while the first mode is ascribed to oxide traps far from the source/channel junction. Although present in smaller numbers, such traps with a larger average impact on the device characteristics are expected to dominate the BTI-induced variability in a large population of nanoscale devices for realistic applications. [ABSTRACT FROM PUBLISHER]

We have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO2) show minimal transconductance degradation (less than 5%), very small \text {V}_{th} shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p$ MOS FinFETs is far superior to that of past generations of planar Ge $p$ MOS devices. These improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology. [ABSTRACT FROM PUBLISHER]

We have measured the low-frequency 1/ f noise of Si0.55Ge0.45 p MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( \textitS {vd} ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device. [ABSTRACT FROM PUBLISHER]