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We show how a CD-TEM (Critical Dimension-Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming. In addition, we demonstrate how detector shadowing can be reduced significantly by using a special specimen holder and modified grids. The recipe, which runs autonomously and automatically, is verified using examples from modern FinFET and non-volatile memory devices.

Transmission electron microscopes have been improved in various ways over the past two decades, giving rise to new characterization techniques. Among the innovations discussed in this article are the introduction of field emission guns, the incorporation of CCD cameras and X-ray detectors, and the use of lens correction systems. Such improvements have had a significant impact on failure analysis through the emergence of new TEM techniques, including precession electron diffraction for grain and strain analysis, noise reduction processing for low dose EELS mapping of ultra-low-k materials, and EDX tomography for elemental 3D imaging of defects on a nanometer scale.

Display Omitted The evolution of CMOS technologies and of the silicidations techniques are described.A peculiar nickel monosilicide defect termed NiSi-Fang is detected and characterized.The NiSiGe formation is investigated on Si, SiGe materials and (100), (111) surfaces.A mechanism for the NiSi-Fang defect formation is proposed.This mechanism involves silicide formation, metal enrichment and metal diffusion. In this paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g. SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. We also investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (100) and (111) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni-Pt-Si-Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6nm.

An improvement in interconnect performance implies a reduction of the resistance-capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

Modulation of Cu interconnect microstructure in a low-k dielectric was achieved at an elevated anneal temperature of 250 °C. In contrast to the unpassivated conventional structure, a TaN metal passivation layer was deposited on the plated Cu overburden surface before annealing at the elevated temperature to prevent stress migration reliability degradation. As compared with the conventional structure annealed at 100 °C, the elevated annealing process enabled further Cu grain growth, which then resulted in an increased Cu grain size and improved electromigration resistance in the interconnects.

We have combined experiments and atomistic modeling in order to better understand the growth and structure of metal films deposited onto sidewalls of trenches and vias. Using x-ray reflectance, atomic force microscopy, and high-resolution transmission electron microscopy to characterize the microstructure and morphology of Ta films grown by magnetron sputtering onto inclined substrates, we find that films deposited at larger incidence angles tend towards columnar microstructure with high roughness and low density. We have used a three-dimensional Monte Carlo model (ADEPT) to simulate the growth process, under conditions close to those investigated experimentally. A binary collision model is included in the Monte Carlo deposition procedure to describe the interaction of energetic particles with the surface. Examination of the film microstructure and morphology resulting from the simulations indicates that the energetic impinging particles are necessary to produce film densities comparable to those found ex...

We show that surface evolution resulting from the deposition of discrete particles is intrinsically different from that produced by continuum processes. The atomistic effects have major consequences, even when observed at macroscopic length scales. We have elucidated some of the atomistic effects by comparing: (i) numerical simulations of thin film deposition using the continuum model, (ii) atomistic (Monte Carlo) models, and (iii) experiments on the sputter deposition of Ta onto a substrate containing etched vias. We have therefore developed a continuum model which incorporates finite atomic length scales. The model incorporates effects of atomic interactions, which lead to the capture of impinging atoms that pass near a point on the film. This capture effect results in “breadloafing” at sharp convex corners where the curvature is high. We have validated our model in idealized two-dimensional simulations and obtained improved qualitative agreement with both experiment and Monte Carlo atomistic simulation...

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical-vapor-deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by raising the deposition pressure. Degree of electromigration (EM) resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6 nm.

The narrowest feature on present-day integrated circuits is the gate oxide—the thin dielectric layer that forms the basis of field-effect device structures. Silicon dioxide is the dielectric of choice and, if present miniaturization trends continue, the projected oxide thickness by 2012 will be less than one nanometre, or about five silicon atoms across1. At least two of those five atoms will be at the silicon–oxide interfaces, and so will have very different electrical and optical properties from the desired bulk oxide, while constituting a significant fraction of the dielectric layer. Here we use electron-energy-loss spectroscopy in a scanning transmission electron microscope to measure the chemical composition and electronic structure, at the atomic scale, across gate oxides as thin as one nanometre. We are able to resolve the interfacial states that result from the spillover of the silicon conduction-band wavefunctions into the oxide. The spatial extent of these states places a fundamental limit of 0.7 nm (four silicon atoms across) on the thinnest usable silicon dioxide gate dielectric. And for present-day oxide growth techniques, interface roughness will raise this limit to 1.2 nm.

We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O/sub 2/ or N/sub 2/O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N/sub B/, for thicknesses other than those measured. We find that the minimum t/sub ox/ required to inhibit boron penetration is always 2-4 nm less when N/sub 2/O-grown gate oxides are used in place of O/sub 2/- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t/sub ox/, incremental variations in oxide thickness result in a large variation in N/sub B/, leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10/sup 11/ cm/sup -2/.

We demonstrate the application of quantitative chemical lattice imaging techniques to a metallic system. The first results establish that the chemical interface between γ and γ′ phases of a nickel-based superalloy can be quantitatively identified.

Thin SiO2 layers were exposed to an HBr/O2 plasma for a variety of short periods, reproducing the over-etching process after polycrystalline Si gate electrodes have been etched and the gate oxide layer is exposed. Samples were transferred under vacuum to an x-ray photoelectron spectrometer for analysis. After relatively thick (>60 A) films were exposed to a 10% O2/HBr plasma at an average ion energy of ∼150 eV, the near-surface region becomes brominated, and the thickness of the film decreases, indicating an etching rate of ∼1–2 A/s. When the starting film thickness is between 10 and 20 A, however, exposure to the plasma results in an increases in the thickness of the film, and is enhanced with the increasing addition of oxygen to the feed gas. At mean ion energies of 40 or 150 eV, the transition from etching to deposition occurs at oxygen additions of ∼1% or ∼8%, respectively. The increase in SiO2 thickness is ascribed mainly to oxidation of the Si at the oxide-substrate interface, and not to deposition ...

We have used off‐axis electron holography at a resolution of 3 A to investigate amorphous bilayer gate oxides consisting of thermal and chemically deposited SiO2. The values of the mean inner potential were measured to be: thermal oxide: (10.51±0.35)V (undensified); (10.65±0.32)V (‘‘densified’’); deposited oxide: (11.19±0.38)V (undensified); (10.58±0.69)V (densified). Exploiting the chemical etch rate differences between different oxides, we have delineated stacked gate oxides consisting of closely similar layers. Our results establish that measurement of thickness differences produced by etching can be used to reveal the densification state of the oxide.

We have used quantitative chemical mapping to determine the chemical abruptness of interfaces in In0.2Ga0.8As/Al0.2Ga0.8As strained multilayers grown by metalorganic chemical vapor deposition. We observe a large difference in the interfacial width, depending on the order in which successive layers are grown; the (Al0.2Ga0.8As on In0.2Ga0.8As) interface is twice as wide as the (In0.2Ga0.8As on Al0.2Ga0.8As).

A demonstration of how to monolithically combine silicon waveguides with MEMS-based phase shifters in a single SOI chip is presented. A folded Mach-Zehnder interferometer switch has been designed and tested. The phase shifters have negligible power consumption and a switching time of 150 µs.

We have performed two-dimensional (2D) and three-dimensional (3D) (axisymmetric) numerical simulations of physical vapor deposition into high aspect ratio trenches and vias used for modern very large-scale integration interconnects. The topographic evolution is modeled using (continuum) level set methods. The level set approach is a powerful computational technique for accurately tracking moving interfaces or boundaries, where the advancing front is embedded as the zero level set (isosurface) of a higher dimensional mathematical function. We have validated both codes against analytic formulas for step coverage. First, we study the 2D case of long rectangular trenches including 3D out-of-plane target flux. The 3D flux can be obtained from molecular dynamics computations, and hence our approach represents a hybrid atomistic/continuum model. Second, we report results of axisymmetric 3D simulations of high aspect ratio vias, which we compare with experimental data for Ti/TiN barrier layers. We find that the s...

Results are described for a gate level technology module developed to produce metal–oxide–semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EBL) using a thermal field-emission EBL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm.