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The interaction between technology and healthcare has a long history. However, recent years have witnessed the rapid growth and adoption of the Internet of Things (IoT) paradigm, the advent of miniature wearable biosensors, and research advances in big data techniques for effective manipulation of large, multiscale, multimodal, distributed, and heterogeneous data sets. These advances have generated new opportunities for personalized precision eHealth and mHealth services. IoT heralds a paradigm shift in the healthcare horizon by providing many advantages, including availability and accessibility, ability to personalize and tailor content, and cost-effective delivery. Although IoT eHealth has vastly expanded the possibilities to fulfill a number of existing healthcare needs, many challenges must still be addressed in order to develop consistent, suitable, safe, flexible, and power-efficient systems that are suitable fit for medical needs. To enable this transformation, it is necessary for a large number of significant technological advancements in the hardware and software communities to come together. This keynote paper addresses all these important aspects of novel IoT technologies for smart healthcare-wearable sensors, body area sensors, advanced pervasive healthcare systems, and big data analytics. It identifies new perspectives and highlights compelling research issues and challenges, such as scalability, interoperability, device-network-human interfaces, and security, with various case studies. In addition, with the help of examples, we show how knowledge from CAD areas, such as large scale analysis and optimization techniques can be applied to the important problems of eHealth. [ABSTRACT FROM AUTHOR]

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC’99 and International Work on Logic and Synthesis’05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits. [ABSTRACT FROM AUTHOR]

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed. [ABSTRACT FROM AUTHOR]

Transistor aging, mostly due to bias temperature instability (BTI), is one of the major unreliability sources at nano‐scale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, standard cells in the library are optimised according to the design time delay; however, because of the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this study, the BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime. The authors find an optimal tradeoff between the increase in the library size and the lifetime improvement by non‐uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that this technique can prolong the circuit lifetime by around 150% with a negligible area overhead. Moreover, the effect of different realistic workloads on the distribution of internal node signal probabilities is investigated. This is done to obtain the sensitivity of the proposed static (design time) approach to different workloads during system lifetime. The results show that the proposed approach is still efficient if the workload changes during the runtime. [ABSTRACT FROM AUTHOR]

The impending Internet of Things (IoT) wave is promising to affect every aspect of our daily lives, ranging from smart things to smart buildings, smart cities, and smart environments. A lot of attention has been devoted to the tsunami of data produced by IoT, and the related means of extracting useful actionable information from it, spawning efforts in Big Data processing and machine learning. Yet, all of this does little to address the need for IoT to capture, interpret, and act on this wall of (noisy) information at the right time, at the right place, and in the right form. Conventional computing systems are a poor match to the needs of this emerging massively distributed real-time system. Hence, alternative computing techniques present an attractive alternative, trading off computational resolution for significant gains in quality-of-service energy efficiency and robustness. This observation is based on the conjecture that most applications related to IoT have an inherent error resilience and are evolutionary (that is, learning-based). Alternative computing strategies may be conceived at every level of the design hierarchy, starting from the device level with novel 3-D nonvolatile memory/logic combinations, or at the architectural level by shifting away from the traditional von Neumann architecture to different computing paradigms such as neuromorphic and/or stochastic computation all the way up to the algorithmic and data representation levels. [ABSTRACT FROM AUTHOR]

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime. [ABSTRACT FROM AUTHOR]