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Chip-level modeling and analysis of electrical masking of soft errors.
- Source :
- 2013 IEEE 31st VLSI Test Symposium (VTS); 2013, p1-6, 6p
- Publication Year :
- 2013
Details
- Language :
- English
- ISBNs :
- 9781467355421
- Database :
- Complementary Index
- Journal :
- 2013 IEEE 31st VLSI Test Symposium (VTS)
- Publication Type :
- Conference
- Accession number :
- 89785575
- Full Text :
- https://doi.org/10.1109/VTS.2013.6548935