1. Low‐cost single event double‐upset tolerant latch design
- Author
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Yiran Xu, Jiangchuan Ren, Dianpeng Lin, Jun Xiao, Weiran Kong, Wenyi Zhu, Shichang Zou, and Jianwei Jiang
- Subjects
010308 nuclear & particles physics ,Computer science ,business.industry ,Reliability (computer networking) ,020208 electrical & electronic engineering ,Clock gating ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,01 natural sciences ,Upset ,High impedance ,Soft error ,Single event upset ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,State (computer science) ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Computer hardware ,Hardware_LOGICDESIGN ,Block (data storage) - Abstract
This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.
- Published
- 2018
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