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Your search keyword '"Chun-Hsien Chien"' showing total 3 results
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3 results on '"Chun-Hsien Chien"'

1. A novel 3D IC assembly process for ultra-thin chip stacking.

Author

Yu-Min Lin, Chau-Jie Zhan, Zhi-Cheng Hsiao, Huan-Chun Fu, Ren-Shin Cheng, Yu-Wei Huang, Shin-Yi Huang, Su-Mei Chen, Chia-Wen Fan, Chun-Hsien Chien, Cheng-Ta Ko, Yu-Huan Guo, Chang-Chun Lee, Tsutsumi, Yoshihiro, Junsoo Woo, Suzuki, Yoshikazu, Sato, Yusuke, Chien-Ting Liu, and Chih-Heng Chao

Published
2014
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2. Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications.

Author

Chen, Erh-Hao, Tzu-Chien Hsu, Cha-Hsin Lin, Tzeng, Pei-jer, Chung-Chih Wang, Shang-Chun Chen, Chen, Jui-Chin, Chien-Chou Chen, Hsin, Yu-Chen, Po-Chih Chang, Yiu-Hsiang Chang, Shin-Chiang Chen, Yu-Ming Lin, Sue-Chen Liao, Cheng-Ta Ko, Chau-Jie Zhan, Hsiang-Hung Chang, Chun-Hsien Chien, Yung-Fa Chou, and Ding-Ming Kwai

Published
2014
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3. Key enabling technologies of 300mm 3DIC process integration.

Author

Pei-Jer Tzeng, Yu-Chen Hsin, Jui-Chin Chen, Shang-Chun Chen, Chien-Ying Wu, Wen-Li Tsai, Chung-Chih Wang, Chi-Hon Ho, Chien-Chou Chen, Yi-Feng Hsu, Shang-Hung Shen, Sue-Chen Liao, Chun-Hsien Chien, Hsiang-Hung Chang, Cha-Hsin Lin, Tzu-Kun Ku, and Ming-Jer Kao

Abstract

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines. [ABSTRACT FROM PUBLISHER]

Published
2012
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