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A low-power 3-9 GHz receiver front-end with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. High stop-band rejection is achieved by using a pre-filter with three finite-transmission zeros, one of which (ωz1=0.9 GHz) is in the low-frequency stop-band and the other two (ωz2 and ωz4) are in the high-frequency stop-band. In the low-gain (LG) mode, the receiver front-end consumes 9.45 mW and achieves high and flat conversion gain (CG) of 25.7±1.5 dB, noise figure (NF) of 6.95 dB, and input third-order intercept point (IIP3) of -8 dBm. To the author's knowledge, this is the lowest-power dissipation (PD) ever reported for a 0.18 mm CMOS receiver front-end with NF smaller than 7 dB, average CG greater than 25 dB and bandwidth wider than or equal to 6 GHz. In the high-gain (HG) mode, the receiver front-end consumes 19.5 mW and achieves high and flat CG of 32.7±1.6 dB, NF of 6.78 dB and IIP3 of -13.5 dBm. In addition, in both the LG and HG modes, the receiver front-end achieves stop-band rejection better than 30 dB for frequencies DC∼1.5 GHz and larger than 12 GHz. [ABSTRACT FROM AUTHOR]

A DC∼10.5 GHz complimentary metal oxide semiconductor (CMOS) distributed amplifier (DA) with flat and low noise figure (NF), flat and high power gain (S21) and small group delay (GD) variation for ultra-wideband (UWB) pulse radio systems using standard 0.18 µm CMOS technology is demonstrated. Flat and low NF was achieved by adopting the proposed resistor capacitor (RC) terminal network with 140 Ω terminal resistance over the frequency band of interest (instead of the traditional 50 Ω terminal resistance or the recently proposed resistor inductor (RL) terminal network) for the gate transmission line. Besides, flat and high S21 was achieved by using cascoded transistors as the gain cell. Over the DC∼10.5 GHz band, the DA consumed 29.16 mW and achieved flat and high |S21| of 10.5±1.4 dB, flat and low NF of 3.2±0.3 dB and excellent phase linearity (the GD variation was only ±13.8 ps), one of the best NF and phase linearity results ever reported for a CMOS DA or wideband low-noise amplifier (LNA) with bandwidth greater than 7.5 GHz. [ABSTRACT FROM AUTHOR]

A CMOS distributed amplifier (DA) with flat and low noise figure (NF), and flat and high gain (S21) is demonstrated. A flat and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S21 was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S21 of 17.5±1.23 dB with an average NF of 3.24 dB over the 3–10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S21 of 10.74±1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW. [ABSTRACT FROM AUTHOR]

A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned by the series-feedback capacitor Cs and the parallel-feedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5–76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature. [ABSTRACT FROM AUTHOR]

A low-power 3.2-9.7 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive bandpass filter (BP-filter) with three finite transmission zeros (in the input terminal), one of which (ωz1=0.9 GHz) is in the low-frequency stop-band and the other two (ωz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of -10 to -39.5 dB, S21 of 9.3±1.5 dB, and an average NF of 6 dB over the 3.2-9.7 GHz band. The measured stop-band rejection is better than 21.6 dB for frequencies DC-2.5 and 11.2-20 GHz. [ABSTRACT FROM AUTHOR]

A 3-9 GHz receiver front-end (RFE) with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. A pre-filter is used to achieve high stop-band rejection and good RF-port input matching. An output buffer with a lowpass filter is used to enhance the conversion gain and to suppress the high-frequency noise and leakage. In the low-noise mode, the RFE consumes 7.2 mW and achieves conversion gain (CG) of 20.21±1.97 dB, a minimum noise figure (NF) of 3.15 dB, and input 1 dB compression point (P1dB) of -16.3 dBm. It is believed that this is the lowest NF ever reported for a CMOS UWB RFE with power consumption lower than 10 mW. In the high-gain mode, the RFE consumes 19.35 mW and achieves a high and flat CG of 32.63±1.55 dB. [ABSTRACT FROM AUTHOR]