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Silicon photonics (SiPh) is a disruptive technology in the field of integrated photonics and has experienced rapid development over the past two decades. Various high-performance Si and Ge/Si-based components have been developed on this platform that allow for complex photonic integrated circuits (PICs) with small footprint. These PICs have found use in a wide range of applications. Nevertheless, some non-native functions are still desired, despite the versatility of Si, to improve the overall performance of Si PICs and at the same time cut the cost of the eventual Si photonic system-on-chip. Heterogeneous integration is verified as an effective solution to address this issue, e.g. through die-wafer-bonding and flip-chip. In this paper, we discuss another technology, micro-transfer printing, for the integration of non-native material films/opto-electronic components on SiPh-based platforms. This technology allows for efficient use of non-native materials and enables the (co-)integration of a wide range of materials/devices on wafer scale in a massively parallel way. In this paper we review some of the recent developments in the integration of non-native optical functions on Si photonic platforms using micro-transfer printing.

There has been an impressive increase in single-chip processing power since the Intel 4004 was launched in 1971. This is usually attributed to Moore's law, but there are additional factors to consider. In understanding the components of prior improvements, we can gain insight into the potential for future improvements and potential limits to scaling.

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer‐scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3‐μm bowing was observed using the 725‐μm‐thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4 × 107 cm−2. For lattice‐matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725‐μm‐thick Si substrate can be used for the large‐scale integration of GaAs on Si with less bowing and low TDD.

Organic semiconducting polymers have opened a new paradigm for soft electronics due to their intrinsic flexibility and solution processibility. However, the contradiction between the mechanical stretchability and electronic performances restricts the implementation of high-mobility polymers with rigid molecular backbone in deformable devices. Here, we report the realization of high mobility and stretchability on curvilinear polymer microstructures fabricated by capillary-gradient assembly method. Curvilinear polymer microstructure arrays are fabricated with highly ordered molecular packing, controllable pattern, and wafer-scale homogeneity, leading to hole mobilities of 4.3 and 2.6 cm2 V−1 s−1 under zero and 100% strain, respectively. Fully stretchable field-effect transistors and logic circuits can be integrated in solution process. Long-range homogeneity is demonstrated with the narrow distribution of height, width, mobility, on-off ratio and threshold voltage across a four-inch wafer. This solution-assembly method provides a platform for wafer-scale and reproducible integration of high-performance soft electronic devices and circuits based on organic semiconductors., Though stretchable semiconducting polymers are advantageous for electronic applications requiring low cost, the low performance of patterned microstructures remains a challenge. Here, the authors realize high mobility, stretchable polymer microstructures via a capillary-gradient assembly method.

As the focus of graphene research shifts from fundamental physics to applications, the scalability and reproducibility of experimental results become ever more important. Graphene has been proposed as an enabling material for the continuing growth of the telecommunications industry due to its applications in optoelectronics; however, the extent of its adoption will depend on the possibility to maintain the high intrinsic quality of graphene when processing it using the industry-standard approaches. We look at the challenges of scalable graphene integration and the opportunities presented by the recent technological advances.

A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

Developing reliable and tunable metamaterials is fundamental to next-generation optical-based nanodevices and computing schemes. In this review, an overview of recent progress made with a unique group of ceramic-based functional nanocomposites, i.e., vertically aligned nanocomposites (VANs), is presented, with the focus on the tunable anisotropic optical properties. Using a self-assembling bottom-up deposition method, the as-grown VANs present great promise in terms of structural flexibility and property tunability. Such broad tunability of functionalities is achieved through VAN designs, material selection, growth control, and strain coupling. The as-grown multi-phase VAN films also present enormous advantages, including wafer scale integration, epitaxial quality, sharp atomic interface, as well as designable materials and geometries. This review also covers the research directions with practical device potentials, such as multiplex sensing, high-temperature plasmonics, magneto-optical switching, as well as photonic circuits.

Vacuum gap λ/2 microwave resonators are demonstrated as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Creating low loss circuits in this geometry is also discussed.

The Von Neumann architecture, defined by strict and hierarchical separation of memory and processor, has been a hallmark of conventional computer design since the 1940s. It is becoming increasingly unsuitable for cognitive applications, which require massive parallel processing of highly interdependent data. Inspired by the brain, we propose a significantly different architecture characterized by a large number of highly interconnected simple processors intertwined with very large amounts of low-latency memory. We contend that this memory-centric architecture can be realized using 3D wafer scale integration for which the technology is nearing readiness, combined with current CMOS device technologies. The natural fault tolerance and lower power requirements of neuromorphic processing make 3D wafer stacking particularly attractive. In order to assess the performance of this architecture, we propose a specific embodiment of a neuronal system using 3D wafer scale integration; formulate a simple model of brain connectivity including short- and long-range connections; and estimate the memory, bandwidth, latency, and power requirements of the system using the connectivity model. We find that 3D wafer scale integration, combined with technologies nearing readiness, offers the potential for scaleup to a primate-scale brain, while further scaleup to a human-scale brain would require significant additional innovations.

The articles in this special section report on the technologies and events that were part of the 31st Annual Hot Chips symposium was held at Stanford University in August 2019.

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.

A high-precision Cu–Cu bonding system for 3-D ICs (3-DICs) fabrication adopting a new precision alignment methodology is proposed. A new pressure profile control system is applied in the thermocompression bonding process. Experimental results show that the alignment capability is 250 nm or better, with similar overlay accuracy ( $\vert $ average $\vert + 3\sigma )$ for permanent bonding. These developments are expected to contribute to the fabrication of future 3-DICs.

In this paper, we report a low-temperature wafer-to-wafer fusion bonding process whose maximum processing temperature is 300C and can potentially be further reduced to 250C. This low-temperature process would enhance the compatibility of the three-dimensional wafer-scale integration technology with the devices and with the temporary adhesive materials that might suffer from high-temperature FBEOL processes. Preliminary experiments are done with blanket 300mm wafers, and characterization results from SAM imaging and mechanical shear test are reported to evaluate the feasibility of the low-temperature fusion bonding process.

Crystalline optical whispering gallery mode resonators made from alkaline earth fluorides can achieve exceptionally large optical finesse, and are used in a variety of applications, from frequency stabilization and narrow linewidth lasers, to low-noise microwave generation or soliton Kerr frequency combs. Here we demonstrate an efficient coupling method to resonators of these materials, which employs photonic integrated waveguides on a chip based on silicon nitride. By converting a mode from silicon nitride to a free-hanging silica waveguide on a silicon chip, coupling to a crystalline resonator is achieved with a high extinction, while preserving a quality factor exceeding 200 million. This compact, heterogeneous integration of ultra-high Q-factor crystalline resonators with photonic waveguides provides a proof of concept for wafer scale integration and robust, compact packaging for a wide range of applications.

We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO2 mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.

In this paper, we present a method to use three-dimensional wafer scale integration (3D-WSI) to build large-scale cognitive systems up to the scale of a human brain (1010 neurons, 1013 synapses). We analyze the effect of scaling by simulating some cognitive systems. The result exhibits attractive properties of the 3D-WSI technology, as compared with the traditional integration scheme using printed circuit boards. At the scale of a human brain, the 3D-WSI system reduces the communication latency by about 10X, while consuming at least 100X less communication power.

International audience; We report on a new cost effective, with a low temperature budget and simple bonding process on silicon, presenting efficient heat spreading and great potentialities in integration. This process is based on a thick electro-plated copper bonding layer through silicon vias and is expected to reduce significantly the bonded device internal temperature. We apply this process to realize 1.55-μm emitting vertical-cavity surface-emitting lasers. We demonstrate continuous wave operation from room temperature up to 55 °C, an internal temperature reduction of 13 °C, and we estimate a decrease of 30% of the overall device thermal impedance.

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications., The wide use of microfluidics for biological analysis demands scalable preparation methods, yet in practice it is very challenging. Here, Wang et al. show a wafer-scale fabrication of nanofluidic chips with single-digit nanometre dimension, which is compatible with standard semiconductor processing.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

One of the main advantages of 2D materials for various applications is that they can be prepared in form of water‐based solutions. The high yield and cost‐effectiveness of this method make them of great interest for printed electronics, composites, and bio‐ and healthcare technologies. However, once deposited on a substrate, etching away these solution‐processed materials is a difficult task, yet crucial for pattern definition and thus device fabrication. In particular, the realization of micrometer‐sized patterns requires mesh and paste optimization when screen‐printed or solvent‐engineered and surface functionalization when inkjet‐printed, both usually involving additional postdeposition steps. These constraints are holding back the integration of these 2D materials in devices and applications. In this work, a method for the fabrication of micrometer‐sized well‐defined patterns in water‐based 2D materials is presented, with an extensive characterization of the films and patterns obtained. The method is ultimately used to create humidity sensors with performance comparable to that of commercial ones. These sensor devices are fabricated onto a 4′ silicon and polyethylene terephthalate (PET) wafers to create all‐graphene humidity sensors that are flexible, transparent, and compatible with current complementary metal–oxide–semiconductor (CMOS) and roll‐to‐roll workflows.

This article surveys recent work in optical switching technologies and presents a fast optical circuit switch that intimately integrates the control electrics at the chip level using a novel wafer-scale heterogeneous integration technique.

Crystalline silicon thin film (c-Si TF) solar cells with an active layer thickness of a few micrometers may provide a viable pathway for further sustainable development of photovoltaic technology, because of its potentials in cost reduction and high efficiency. However, the performance of such cells is largely constrained by the deteriorated light absorption of the ultrathin photoactive material. Here, we report an efficient light-trapping strategy in c-Si TFs (~20 μm in thickness) that utilizes two-dimensional (2D) arrays of inverted nanopyramid (INP) as surface texturing. Three types of INP arrays with typical periodicities of 300, 670, and 1400 nm, either on front, rear, or both surfaces of the c-Si TFs, are fabricated by scalable colloidal lithography and anisotropic wet etch technique. With the extra aid of antireflection coating, the sufficient optical absorption of 20-μm-thick c-Si with a double-sided 1400-nm INP arrays yields a photocurrent density of 39.86 mA/cm(2), which is about 76 % higher than the flat counterpart (22.63 mA/cm(2)) and is only 3 % lower than the value of Lambertian limit (41.10 mA/cm(2)). The novel surface texturing scheme with 2D INP arrays has the advantages of excellent antireflection and light-trapping capabilities, an inherent low parasitic surface area, a negligible surface damage, and a good compatibility for subsequent process steps, making it a good alternative for high-performance c-Si TF solar cells.

Differential on-chip microstrip and slot-ring antennas with a quartz superstrate are presented for wafer-scale silicon systems. The antennas are fed at the nonradiating edge, which is compatible with differential coupled-lines, and are built on a 0.13-μ m CMOS process with a layout that meets all the metal density rules. A high radiation efficiency is achieved using a 100- μm quartz superstrate placed on top of the silicon chip. Both antennas have a measured gain varies from about 2 to 3 dBi at 91-94 GHz, with a - 10-dB S11 bandwidth of 7-8 GHz and a simulated radiation efficiency of >;50%. The designs are compatible with single- and multielement transceivers, and with wafer-scale imaging systems and power-combining arrays.

Silicon substrates form the foundation of modern microelectronics. Whereas the first 50 years of silicon wafer technology were primarily driven by the microelectronics industry, applications in photovoltaics (PV) also promise to drive new advances in silicon wafer technology over the next ten years. In the first part, we review the historical development of semiconductor silicon wafer technology and highlight recent technical advances in bulk crystal growth and wafering technologies, including the development of silicon-on-insulator (SOI) technologies and ultrathin wafers. We then discuss technologies that could take us beyond the current capabilities of complementary metal-oxide-semiconductor (CMOS) devices. In the second part, we review silicon manufacturing for PV applications and some unique wafering technology challenges in that field. Finally, we summarize industry roadmaps and product needs highlighting key technical areas which promise to shape the future of silicon wafer technologies in the coming decades.

What is the future of integrated inductor design on silicon for power conversion applications at frequencies up to 100 MHz-is it magnetic-core or air-core inductors. This study presents measured results for two microfabricated inductors (magnetic core and air core), which have been designed to operate at 20 MHz and occupy a substrate area of less than 10 mm2. The inductor technology and design are briefly discussed. An optimized inductor design study is, then, presented. Both magnetic-core and air-core inductor designs are compared and evaluated, in terms of inductance and efficiency per unit area for frequencies up to 100 MHz. The design of the microinductors is discussed and an analytical design optimization program is used to model the devices for the maximum efficiency and inductance. The introduction of laminations with high-frequency core inductors will also be examined within the study. A 100 MHz magnetic-core inductor design with three laminations gives a 36 nH inductance, with 96.4% efficiency and an area of 3 mm2 . A comparable air-core design also gives a 36 nH inductance, with 93.45% efficiency and an area of just 2.6 mm2.

This paper presents on-chip slot-ring and horn antennas for wafer-scale silicon systems. A high efficiency is achieved using a 100-μm quartz superstrate on top of the silicon chip, and a low-loss microstrip transformer using the silicon back-end metallization. A finite ground plane is also used to reduce the power coupled to the TEM mode. The slot-ring and 1-λ02 horn achieve a measured gain of 0-2 and 6-8 dBi at 90-96 GHz, respectively, and a radiation efficiency of ~50%. The horns achieve a high antenna gain without occupying a large area on the silicon wafer, thus resulting in a low-cost system. The designs are compatible with either single- or two-antenna transceivers, or with wafer-scale imaging systems and power-combining arrays.

In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13% reduction in thermal resistance.

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.

WLP (Wafer level packaging) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to establish electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and TSV (Through Silicon Via). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Key fabrication processes include glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is needed for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.

In this paper, we describe a new wafer yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.

This paper validates a proposed job release methodology and experimentally investigates the impact of production control methodologies and system factors on wafer fab performance in terms of average cycle time, standard deviation of cycle time, average lateness, WIP inventory and fab output by simulating a wafer fab of Chartered Semiconductor Manufacturing Ltd (Chartered) and statistically analyzing the experimental results using t-test and ANOVA. A full factorial design of experiment is conducted to evaluate the performance of three job release methodologies, three dispatching rules and three greedy levels of batching policy under different system environmental settings differentiated by fab output level and machine unreliability level. Based on the experimental results, the proposed job release methodology WIPLOAD control (WIPLCtrl) appears to be very efficient to be able to potentially improve all the considered performance measures simultaneously. The advantage of WIPLCtrl is robust to the change of system environmental conditions. In contrast, the improvement brought by a dispatching rule on a certain performance measure might cost the deterioration of other performances. Considering the relative impact on the fab performance, job release control appears to be the most important production control factor in comparison with dispatching and batching policy, especially when the system is operating on a high output level and/or with a high system variability level caused by machine unreliability.

This paper reports a MEMS vacuum package with vertical feedthroughs formed in a glass substrate all at the wafer level. This approach satisfies requirements for MEMS vacuum packages, including small size, vacuum/hermetic capability, sealed and low parasitic feedthroughs, wafer-level processing, compatibility with most MEMS processes, and low cost. It also enables flip-chip solder attachment to a PC board. The package has an integrated micro-Pirani gauge on a glass substrate for in situ monitoring, a silicon cap, and vertical feedthroughs through the glass. The integrated Pirani gauge has 0.6 milli-torr resolution at 0.1 torr and 0.2 torr resolution at 100 torr. Using the Pirani gauge, the fabricated vacuum package is characterized. The package has maintained ~33 torr base pressure with plusmn1.5 torr uncertainty for more than four months without a getter. The long-term measured pressure uncertainty is from the measurement setup and environment, and can be improved using a getter inside the package. [2007-0160]