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Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration
- Source :
- IEEE Transactions on Electron Devices. 64:5065-5072
- Publication Year :
- 2017
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2017.
-
Abstract
- A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.
- Subjects :
- 010302 applied physics
Materials science
Wafer-scale integration
business.industry
Stacking
02 engineering and technology
Adhesion
021001 nanoscience & nanotechnology
Electrostatics
Chip
01 natural sciences
Clamping
Electronic, Optical and Magnetic Materials
Reliability (semiconductor)
parasitic diseases
0103 physical sciences
Electronic engineering
Optoelectronics
Wafer
Electrical and Electronic Engineering
0210 nano-technology
business
Subjects
Details
- ISSN :
- 15579646 and 00189383
- Volume :
- 64
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Electron Devices
- Accession number :
- edsair.doi...........7add33cd8262993861f991c0b5e56e25