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2. Fuse on PiN silicon diode monolithic integration for new fail-safe power converters topologies

Author

Oumaziz, Amirouche, Richardeau, Frédéric, Bourennane, Abdelhakim, Sarraute, Emmanuel, Imbernon, Éric, Ghannam, Ayad, Richardeau, Frédéric, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Service Techniques et Équipements Appliqués à la Microélectronique (LAAS-TEAM), 3DiS Technologies, and Serge Pierfederici and Jean-Philippe Martin - Editors

Subjects
monolithic integration, TCAD, Short-Circuit, [SPI.NRJ]Engineering Sciences [physics]/Electric power, fuse, Safety Design, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fail-safe converter, short-circuit protection, safe inverter leg, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; In this paper, a first concept of monolithic integration of a fuse on a silicon PiN diode is realized and experimentally characterized. An integrated fuse on PiN diode allows fast cutoff , with low I²T (less than 2 A².s) and short pre-arcing times (4 to 6 µs). These fuse-on-diode components are intended for failsafe topologies power converter, aiming for more compact and reliable applications. The fuses were electrothermally designed using Comsol Multiphysics™ and TCAD Sentaurus™ simulations were carried out to study their integration on PiN diodes. Characterization and experimental tests were carried out after components realization.

Published
2022
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3. Modélisation électrothermique compacte des modes de défaillance du Mosfet SiC en régime extrême de court-circuit. Application au développement d'une protection intégrée pour convertisseur sécurisé à tolérance de panne

Author

Boige, François, Richardeau, Frédéric, Lefebvre, Stéphane, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Rennes (ENS Rennes)-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS)-Ecole Normale Supérieure Paris-Saclay (ENS Paris Saclay)-Université Gustave Eiffel-CY Cergy Paris Université (CY), ANR-15-CE05-0010,HIT-TEMS,Nouvelle technologie d'intégration hybride d'un convertisseur entrelacé multiniveaux sûr et reconfigurable sous contraintes thermiques et CEM(2015), Richardeau, Frédéric, and Nouvelle technologie d'intégration hybride d'un convertisseur entrelacé multiniveaux sûr et reconfigurable sous contraintes thermiques et CEM - - HIT-TEMS2015 - ANR-15-CE05-0010 - AAPG2015 - VALID

Subjects
court-circuit, modélisation compacte, driver, régime extrême, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Mosfet SiC, protection, modes de défaillance, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

National audience; Le Mosfet SiC de puissance présente des propriétés singulières en régime de court-circuit (CC) telles qu’un courant de fuite de grille important, un fort courant de saturation et deux modes de défaut complémentaires dont l'un est sécurisant (fail-to-open) sous certaines conditions. Ce papier présente un modèle électro-thermique compact original représentatif des singularités du composant. Une analyse technologique poussée de la défaillance a permis de modéliser et de comprendre ses modes de défaut. Enfin, un nouveau circuit de protection contre les court-circuits utilisant le courant de fuite de grille comme indicateur observable est présenté et validé.

Published
2021

4. Protection rapide et robuste contre les courts-circuits internes de convertisseurs à base de MOSFETs SiC

Author

Barazi, Yazan, Boige, François, Rouger, Nicolas, Blaquière, Jean-Marc, Vinnac, Sébastien, RICHARDEAU, Frédéric, Richardeau, Frédéric, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Convertisseurs Statiques (LAPLACE-CS), and Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3)

Subjects
court-circuit, [SPI.NRJ]Engineering Sciences [physics]/Electric power, charge de grille, fuite de grille, détection et protection, MOSFET SiC, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

National audience; Les MOSFETs SiC ont un court temps de tenue au court-circuit par rapport aux IGBTs Silicium. Pour répondre à cette problématique, trois méthodes de détection originales sont proposées et ont été mises en oeuvre. Elles sont basées sur un diagnostic de signaux basse-tension accessibles et traités directement depuis le driver (IG, VGS), de manière indépendante du temps. La première méthode est dédiée aux MOSFETs SiC et repose sur la détection d'un niveau anormal de la fuite de grille sur la durée de conduction. La seconde est plus générale et plus rapide car elle utilise la surveillance de la charge de grille sur le cycle de commutation, connues sous le nom de « gate charge monitoring ». Cette dernière méthode est déjà connue pour les IGBTs Silicium mais encore peu développée pour les MOSFETs SiC. Les deux méthodes ont été expérimentées en technologie CMS et évaluées en termes de temps de réponse de robustesse, avec un temps de détection de 130 ns, pour une résistance de grille de 10 Ohms, en présence d'une capacité de grille de 1.7 nF. La troisième méthode de détection est intégrée sur puce en technologie CMOS. Elle est basée sur l'étude de la dérivée temporelle de VGS. La puce conçue regroupe les fonctions de commande rapprochée, de détection et de protection.

Published
2021

7. Global electro-thermal modelling and circuit-type simulation of SiC Mosfet power devices in short-circuit operation for critical system analysis

Author

Boige, François, RICHARDEAU, Frédéric, Lefebvre, Stéphane, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT), Convertisseurs Statiques (LAPLACE-CS), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Laboratoire d’Océanologie et de Géosciences (LOG) - UMR 8187 (LOG), Institut national des sciences de l'Univers (INSU - CNRS)-Université du Littoral Côte d'Opale (ULCO)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD [France-Nord]), Laboratoire de Ressources Halieutiques, Institut Français de Recherche pour l'Exploitation de la Mer (IFREMER), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Centre d'enseignement Cnam Paris (CNAM Paris), Conservatoire National des Arts et Métiers [CNAM] (CNAM), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Pagès, Nathalie, Richardeau, Frédéric, Convertisseurs Statiques (CS), École normale supérieure - Rennes (ENS Rennes)-Université Paris-Sud - Paris 11 (UP11)-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Gustave Eiffel (UNIV GUSTAVE EIFFEL)

Subjects
model validation, MOSFET, silicon carbide, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, short-circuit, electrothermal simulation, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; The purpose of this paper is to present, for the first time, a global transient electrothermal model and simulation results of commercially recent silicon carbide (SiC) power MOSFET devices. The developed models aim is faithfully transposing specifically experimental short-circuit (SC) behaviour of the studied components, ready-to-use for the analysis of an inverter-leg malfunctioning. After extensive experimentation, a thermal model of the SiC die allows to develop models of gate-leakage current and drain-source current during SC. After verifying the robustness of the proposed models, an original circuit-type with an easy implementation is performed using a commercial circuit simulation tool.

Published
2017

9. Switching Optimization of WBG Power Devices on Inverter Leg

Author

Rossignol, Timothé, RICHARDEAU, Frédéric, Blaquière, Jean-Marc, Risaletto, Damien, Senghor, F., Cousineau, Marc, AULAGNIER, GUILLAUME, Cousineau, Marc, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Technocentre Renault [Guyancourt], RENAULT, University of Toulouse, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique de Toulouse (INPT-ENSEEIHT), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor (Freescale), and Freescale semiconductor

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, Switching optimization, Hardware_INTEGRATEDCIRCUITS, Wide band gap devices, Inverter leg, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; In this paper the authors are interested by the switching optimisation of a SiC Power MOSFET in an inverter leg. The authors explain their efforts to build a test-bench that allows the extremely fast switching measurement of this WBG (Wide Band-Gap) component. Then trade-off curves between the dv/dt versus the switching energy are presented. The parameters are the external gate resistor and an additional gate-drain capacitor. Finally, basic dv/dt models are proposed and compared with the experimental results.

Published
2013

10. Survey on fault operation on multilevel inverters

Author

Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. (TIEG) - Terrassa Industrial Electronics Group, Lezana, Pablo, Pou Félix, Josep, Meynard, Thierry A., Rodríguez, José, Ceballos Recio, Salvador, Richardeau, Frédéric, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. (TIEG) - Terrassa Industrial Electronics Group, Lezana, Pablo, Pou Félix, Josep, Meynard, Thierry A., Rodríguez, José, Ceballos Recio, Salvador, and Richardeau, Frédéric

Abstract

This paper is related to faults that can appear in multilevel (ML) inverters, which have a high number of components. This is a subject of increasing importance in high-power inverters. First, methods to identify a fault are classified and briefly described for each topology. In addition, a number of strategies and hardware modifications that allow for operation in faulty conditions are also presented. As a result of the analyzed works, it can be concluded that ML inverters can significantly increase their availability and are able to operate even with some faulty components., Peer Reviewed, Postprint (published version)

Published
2010

12. Fault tolerant-topology and controls for a three-level hybrid neutral point clamped-flying capacitor converter.

Author

Abdelghani, Hafedh Ben, Abdelghani, Afef Bennani Ben, Richardeau, Frédéric, Blaquière, Jean-Marc, Mosser, Franck, and Slama-Belkhodja, Ilhem

Subjects
FAULT tolerance (Engineering), ON-chip charge pumps, CASCADE converters, ELECTRIC fault location, TOPOLOGY
Abstract

This study details a three-level hybrid fault-tolerant converter. The definition of an original decoupling solution between the fourth flying capacitor (FC) leg and the three neutral point (NP) clamped-based phases overcomes topology hybridisation issues. Under normal conditions, a control strategy of the FC-based leg leads to a converter NP voltage balance, and decreases the DC side capacitors' volume and cost. Under fault conditions, the presented fault isolation and converter reconfiguration strategies generate a post-fault converter, which is able to operate safely with the added FC-based leg. The proposed topology is an interesting trade-off between converter fault-tolerant capability and its complexity and offers the ability to be simply reconfigured and controlled in the case of switch fault occurrence. Two operation modes under fault conditions are presented and their performances are shown and discussed through simulation results and first experimental tests. [ABSTRACT FROM AUTHOR]

Published
2016
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16. Evaluation of Vce Monitoring as a Real-Time Method to Estimate Aging of Bond Wire-IGBT Modules Stressed by Power Cycling.

Author

Smet, Vanessa, Forest, François, Huselstein, Jean-Jacques, Rashed, Amgad, and Richardeau, Frédéric

Subjects
SEMICONDUCTORS, VOLTAGE-frequency converters, REAL-time control, TRANSISTORS, BIPOLAR transistors, INSULATED gate bipolar transistors
Abstract

The supervision of semiconductor power devices in operation demonstrates an obvious interest to improve the operating safety of electronic power converters used in critical applications. Unfortunately, this is a significant challenge due to the variability of stress conditions on the one hand and to the difficulty to implement accurate measurement systems in power stages on the other. Using VCE measurement as a real-time supervision method is evaluated here by using aging test results obtained on insulated gate bipolar transistor (IGBT) modules stressed by power cycling. These results are related to the aging of bond wires and metallization, on the top part of the module. Results were obtained in original test benches whose characteristics are overviewed briefly in the first part of this paper, along with a description of test conditions. The second part presents selected results extracted from a larger work and focusing on the VCE evolution with respect to degradations of the module's top part. Their analysis highlights the potential of VCE measurement. The last part proposes the principle of a specific system able to achieve real-time VCE supervision in the test benches in operation. [ABSTRACT FROM PUBLISHER]

Published
2013
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17. New Self-Switching Converters.

Author

Richardeau, Frédéric, Roux, Nicolas, Foch, Henri, Laur, Jean-Pierre, Breil-Dupuy, Marie, Sanchez, Jean-Louis, and Capy, Florence

Subjects
*ELECTRIC current converters, *ELECTRIC power supplies to apparatus, *DC-to-DC converters, *ELECTRIC inverters, *FREQUENCY changers
Abstract

This paper presents an original concept in which integrated over-voltage and/or over-current protections of power devices are used to produce a self-switching operation. Such a commutation is shown as a possible combination with conventional forced-switching and spontaneous-switching to simplify direct regenerative ac-dc conversion, insulating dc-ac-dc conversion and finally direct ac-ac conversion. Experimental results prove the feasibility of the concept through which the self turn-off operation is likely to offer the best practical gains. [ABSTRACT FROM AUTHOR]

Published
2008
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18. Architecture Complexity and Energy Efficiency of Small Wind Turbines.

Author

Mirecki, Adam, Roboam, Xavier, and Richardeau, Frédéric

Subjects
WIND turbines, POWER (Mechanics), TORQUE, SPEED, TURBINES
Abstract

The power characteristics of wind turbines are non- linear. It is particularly true for vertical-axis turbines whose provided power is very sensitive to the load. Thus, controlling the operating point is essential to optimize the energetic behavior. Several control strategies (maximum power point tracking) can be used for the energy conversion. If the wind-turbine characteristic Cp (λ) is supposed to be a priori known, it can be used for optimal control of the torque, speed, or system output power. On the contrary, if this characteristic is unknown, an operational seeking algorithm such as fuzzy logic has to be implemented. Several structures with different associated complexity degrees can be used, in particular, the structure of the ac-dc conversion, which can be either a pulsewidth-modulation voltage-source rectifier or a simple diode bridge. A comparative study of the corresponding control strategies and architectures is proposed in this paper regarding the tradeoffs between structure complexity and energy efficiency. The analysis is based on simulations and experiments. [ABSTRACT FROM AUTHOR]

Published
2007
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19. Use of Opposition Method in the Test of High-Power Electronic Converters.

Author

Forest, François, Huselstein, Jean-Jacques, Faucher, Sébastien, Elghazouani, Mohamed, Ladoux, Philippe, Meynard, T. A., Richardeau, Frédéric, and Turpin, Christophe

Subjects
CASCADE converters, ELECTRIC current converters, ELECTRONICS, ELECTRONIC modulation, POWER resources, ELECTRIC power
Abstract

The test and the characterization of medium or high-power electronic converters, under nominal operating conditions, are made difficult by the requirement of high-power electrical source and load. In addition, the energy lost during the test may be very significant. The opposition method, which consists of an association of two identical converters supplied by the same source, one operating as a generator, the other as a receptor, can be a better way to do these test. Another advantage is the possibility to realize accurate measurements of the different losses in the converters under test. In the first part of this paper, the characteristics of the method concerning loss measurements are compared to those of the electrical or calorimetric methods, then it is shown how it can be applied to different types of power electronic converters, choppers, switched mode power supplies, and pulsewidth modulation inverters. In the second part, different examples of studies conducted by the authors, and using this method, are presented. They have varying goals, from the test of soft-switching inverters to the characterization of integrated gate-commutated thyristor (IGCT) devices mounted into 2-MW choppers. [ABSTRACT FROM AUTHOR]

Published
2006
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20. Fault Management of Multicell Converters.

Author

Turpin, Christophe, Baudesson, Philippe, Richardeau, Frédéric, Forest, François, and Meynard, Thierry A.

Subjects
FAULT location (Engineering), CONVERTERS (Electronics)
Abstract

Examines the consequences of faults in hard-switching and soft-switching multicell converters. Use of different arrangement of components; Differences of consequence of faults; Description of solutions to minimize the consequences of major faults.

Published
2002
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21. Multicell Converters: Derived Topologies.

Author

Meynard, Thierry A., Foch, Henri, Forest, François, Turpin, Christophe, Richardeau, Frédéric, Delmas, Laurent, Gateau, Guillaume, and Lefeuvre, Elie

Subjects
POWER electronics, ALTERNATING currents
Abstract

Analyzes the properties of multicell converters. Analysis of the different ways to introduce soft switching in multicell converters; Concept of distributing power over several switches; Description of direct ac-ac converters using the multicell approach.

Published
2002
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22. V DS and V GS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode.

Author

Barazi, Yazan, Richardeau, Frédéric, Jouha, Wadia, and Reynes, Jean-Michel

Subjects
*METAL oxide semiconductor field-effect transistors, *FAILURE mode & effects analysis, *SILICON carbide, *TEMPERATURE measurements, *FAILURE analysis
Abstract

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON. [ABSTRACT FROM AUTHOR]

Published
2021
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23. Predictive gate ageing-laws of SiC MOSFET under repetitive short-circuit stress

Author

F. Richardeau, Y. Barazi, and Richardeau, Frédéric

Subjects
Gate-Ageing Modelling, SiC Mosfet, Condensed Matter Physics, Wide Band Gap Power Device Robustness, Atomic and Molecular Physics, and Optics, [SPI.TRON] Engineering Sciences [physics]/Electronics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Short-Circuit, Gate-Ageing, Wide Band Gap Power Device Reliability, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Failure-Mode, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

This paper proposes SiC MOSFET gate ageing-laws under repetitive short-circuit stress. Based on analytical studies, physical forms and preconditioning data, numerical fitting based on stress variables T j, T Pulse Gate Damage % and E sc is proposed. Accuracy and prediction capabilities of ageing-laws have been evaluated and compared. Resulting in suggesting a new ageing-law based on T Al_Top metal-source. This one gives the best fitting accuracy. Finally, the ageing-law based directly on the short-circuit energy E sc appears to have the best in prediction capability.

Published
2022

24. Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

Author

Yazan Barazi, Nicolas Rouger, Jean-Marc Blaquiere, Frédéric Richardeau, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Richardeau, Frédéric, Centre National de la Recherche Scientifique (CNRS), and Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
Fault under load, Computer science, 020209 energy, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Gate-charge, Robustness (computer science), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, SiC MOSFET, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Robustness, Hard switching fault, Power device, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Charge (physics), Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), [SPI.NRJ] Engineering Sciences [physics]/Electric power, Hardware_LOGICDESIGN
Abstract

International audience; This paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond-150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board).

Published
2021
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25. Repetitive short circuit capability of SiC MOSFET at specific low gate-source voltage bias for more robust extreme operation

Author

Wadia Jouha, Stephane Azzopardi, Frédéric Richardeau, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique (Toulouse) (Toulouse INP), Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Safran Tech, and Richardeau, Frédéric

Subjects
Materials science, 02 engineering and technology, 01 natural sciences, MESH: Robustness, Short circuit, Gate depolarization, SiC MOSFET, Failure analysis, Modelling Experiments, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Voltage source, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Power density, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Insulated-gate bipolar transistor, Condensed Matter Physics, Chip, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, 13. Climate action, Optoelectronics, Junction temperature, business, Short circuit, [SPI.NRJ] Engineering Sciences [physics]/Electric power, Voltage
Abstract

International audience; This paper presents short-circuit (SC) performance of a commercial silicon-carbide (SiC) MOSFET device under repetitive SC stress at high drain source voltage. Two protocols are investigated to evaluate the impact of gate-source voltage (VGS) depolarization and SC duration (TSC) reduction. The VGS depolarisation provides a power density reduction and allows to preserve a secure failure mode (FTO: Fail To Open) with an increase of the short circuit duration TSCmax. The results demonstrate that SiC MOSFET VGS depolarization does not reduce SC cycling capability at TSCmax. However, using VGS depolarization allows to get performance close to IGBT robustness levels with almost 1000 cycles @TSC=10µs. The simulation of the chip temperature evolution during SC tests suggests that the degradations stay attributed to the increase of junction temperature (TJ) during the SC cycles, which leads to the fusion of the top Al inducing cracks into the thick oxide.

Published
2021
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26. Fast cut-off, low I 2 T and high temperature monolithic on-chip fuse on silicon substrate for new fail-safe embedded power switch

Author

Céline Combettes, A. Bourennane, Vincent Bley, Ayad Ghannam, Amirouche Oumaziz, Frédéric Richardeau, Emmanuel Sarraute, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), 3DiS Technologies, Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Toulouse - Jean Jaurès (UT2J), and Richardeau, Frédéric

Subjects
Materials science, Silicon, chemistry.chemical_element, 02 engineering and technology, Substrate (electronics), 010402 general chemistry, 7. Clean energy, 01 natural sciences, Thermal insulation, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, 3D finite elements method, fuse design, Steady state, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, 0104 chemical sciences, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), Power Converters, Semiconductor, chemistry, On-chip fuse, Fuse (electrical), Optoelectronics, 0210 nano-technology, business, [SPI.NRJ] Engineering Sciences [physics]/Electric power, Voltage
Abstract

Prix du meilleur article lors de la conférence « 32nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis » - ESREF 2021; International audience; In this paper, a first concept of monolithic semiconductor fuses on silicon substrate, is realized and experimentally characterized. These new compact devices are, able to perform fast and irreversible current cutoff at medium voltage (200V), relatively high current (10A), with very low pre-arcing time (~ 4 µs to 5 µs). The fuses are intended for fail-safe power converter capabilities applications. Design and 3D simulation by finite elements method, taking into account static and dynamic specifications have been carried out. Thermal management in steady state is improved by dielectric epoxy thermal insulation under each constriction of the fuse. Implementation and practical tests are reported.

Published
2021
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27. Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Author

Wadia Jouha, Stephane Azzopardi, Frédéric Richardeau, Richardeau, Frédéric, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, and Safran Tech

Subjects
Materials science, Thermal runaway, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, Planar, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Voltage source, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Power density, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), Optoelectronics, business, Failure mode and effects analysis, Short circuit, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe "Fail-To-Open" (FTO) mode in planar power SiC MOSFET devices under shortcircuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm²) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e VBRmin / 2. The boundary of the power density between FTO and "Fail-To-Short" (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

Published
2021
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28. Monolithic asymmetric switching cells integrated on vertical multi-terminal Si power chips

Author

Frédéric Richardeau, Adem Lale, A. Bourennane, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J), Convertisseurs Statiques (CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Convertisseurs Statiques (LAPLACE-CS), IRT Saint Exupéry - Institut de Recherche Technologique, Richardeau, Frédéric, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
Power management, business.industry, Computer science, 020209 energy, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, 02 engineering and technology, Insulated-gate bipolar transistor, Decoupling capacitor, 7. Clean energy, Manufacturing cost, law.invention, Capacitor, Reliability (semiconductor), law, Power module, 0202 electrical engineering, electronic engineering, information engineering, Power semiconductor device, business, ComputingMilieux_MISCELLANEOUS, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; Power electronic converters (power modules) are essential devices for high efficient power management. Applications are ever more demanding in terms of compactness, reliability and cost reduction with increased intrinsic performance. The current technology of standard power modules, that use IGBT chips, is reaching its limits and the margins for improvement do not allow to meet the short-term emerging needs. Indeed, in a standardpower module, each switching cell requires the manufacture of two chips and two wirebonds for interconnections. Each wirebond is a source of stray inductance and constitutes a limiting factor of electrical performance, a source of an increase in the level of electrical stress and of reliability problems. It is customary to place a decoupling capacitor on the power supply terminals of the switching cell. This capacitor makes it possible to compensate the stray inductance prior to the switching cell but itdoesn’t compensate in any way the stray inductance within the switching cell. This paper proposes for the first time a concept of an ultimate monolithic wire-bondless switching cell that allows to suppress the wirebonds within the switching cell and therefore minimize the stray inductance value. Consequently, it is suited for the emerging applications requiring to achieve simultaneously: reliability, compactness, intrinsic performance and reduced manufacturing cost.

Published
2019

29. Impact of bidimensional physical modeling multicellular of power semiconductor device on the evaluation of the reliability package applied to automotive

Author

EL BOUBKARI, Kamal, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Université Sciences et Technologies - Bordeaux I, ERIC WOIRGARD, FIDEA, El Boubkari, Kamal, Woirgard, Eric, Azzopardi, Stéphane, Locatelli, Marie-Laure, Bontemps, Serge, Khatir, Zoubir, Planson, Dominique, and Richardeau, Frédéric

Subjects
Modélisation éléments finis, Failure analysis, Semiconducteurs, Tcad-sentaurus, Short-circuit, Extractions de paramètres, Igbt, [SPI.TRON] Engineering Sciences [physics]/Electronics, Modelling, Convertisseurs électriques, [SPI.TRON]Engineering Sciences [physics]/Electronics, Thermographie infrarouge, Court-circuit, Semiconductors, Finite element, Véhicules électriques hybrides Véhicules électriques, Modélisation, Analyse de défaillance, Extrations de paramètres, Infrared thermography, Fiabilité, Semi conducteurs, Parameters extractions, Thermographie infrouge, Eléments finis
Abstract

On board electric vehicles (EVs) and hybrid (HEV), the functions of traction is provided by power electronic converters. These consist of power modules (IGBT or MOSFET). During their operation, these modules are sometimes subjected to high electrical and thermal stresses that lead to failure or even destruction.The first objective will be to achieve experimental bench to study ageing IGBT modules under extreme operating conditions ( short circuit mode). Thus, we evaluate the various indicators of ageing to predict component failure. Topics will also follow the ageing or degradation initiated on IGBT components by infrared thermography. The second objective is to model and simulate by finite element different IGBT structures to validate the models in static and dynamic operation. The advantage of multicellular approach to the single cell approach will be highlighted., A bord des véhicules électriques (VE) et Hybrides (VEH), les fonctions de tractions sont assurées par des convertisseurs électroniques de puissances. Ces derniers sont constitués de module de puissance (IGBTs ou MOSFETs). Au cours de leur fonctionnement, ces modules sont parfois soumis à de fortes contraintes électriques et thermiques qui amènent à une défaillance ou même à une destruction. Le premier objectif sera de réaliser un banc expérimentale permettant d'étudier le vieillissement des modules IGBTs en régîmes extrêmes de fonctionnement (mode de court-circuit). Ainsi, nous évaluerons les différents indicateurs de vieillissements permettant de prédire la défaillance du composant. Il sera question aussi de suivre le vieillissement ou une dégradation initié sur les composants IGBTs par thermographie infrarouge. Le second objectif sera de modéliser et simuler par éléments finis différentes structures d'IGBTs, afin de valider les modèles en fonctionnement statique et dynamique. L'avantage de l'approche multicellulaire par rapport à l'approche unicellulaire sera mis en avant.

Published
2013

30. Comparison between ig Integration and vgs Derivation methods dedicated to fast Short-Circuit 2D-Diagnosis for Wide Band Gap Power Devices

Author

Barazi Yazan, Nicolas Rouger, Frédéric Richardeau, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, IRT Saint Exupéry - Institut de Recherche Technologique, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Richardeau, Frédéric, and Convertisseurs Statiques (CS)

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.NRJ] Engineering Sciences [physics]/Electric power, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; This paper presents and compares two original high speed protection circuits, ig integration and vgs derivation methods against Short Circuit (SC) types, Hard Switch Fault (HSF) and Fault Under Load (FUL). Since the gate-drain capacitor Cgd of a power device depends on vds, it can become an original native sensor to monitor the switching operation and so detect unwanted vds transition or absence of vds transition by monitoring only vgs. Using only low-voltage monitoring is an essential step to integrate fast and embedded new detection methods on an ASIC gate driver. This Cgd capacitor plays a major part in the two detection methods. The first method is based on dedicated two-dimension monitoring of the gate charge transferred in a time interval combined with gate voltage monitoring. The second method consists of the reconstruction of the dvgs/dt by means of a capacitive current sensing to provide the vgs derivation combined with the vgs monitoring. Comparison and simulation of the methods based on a C2M0025120D SiC MOSFET device under LTspice™ are made to verify the validity of the methods. In terms of detection speed of the SC, a detection time of 300ns is obtained for both methods. Both methods are easy to design, and to integrate. However, the robustness and the speed of detection trade-off of all these methods will be analyzed and compared relatively to the critical functionalities.

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