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This article contains the results of research on the topical problem of highly sensitive express registration of biological objects using field-effect transistors with the surface open for analyte access, which are made based on silicon-on-insulator (SOI) films. The possibilities of dielectrophoretic effects for controlling the concentration of the analyte in the area of sensory elements are considered on the example of the indication of viruses of nuclear polyhedrosis and vaccinia. It is shown that the use of the dielectrophoresis (DEPh) effect makes it possible to solve (1) the key tasks for creating sensor systems: increasing the detecting ability, as well as exrtacting and verifying the signal from the target particles; and (2) the fundamental task: determining the charge state of the analyte in solutions without modifying the sensors’ surface. The problems and prospects of the mass application of nanowire (NW) biosensors, including those with the dielectrophoretic effect, in biotechnology, virology, etc., are discussed.

Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.

The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.

The effect of the source/drain parasitic resistance (RS) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on RS has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.

Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET.

This paper discusses the nature of degradation by NBTI effect in MOS junctionless devices when varying the density of interface traps and surface potential. The data obtained in simulations are compared with results from physical devices and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping concentration and the gate bias are varied.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

We propose an efficient method for subband calculations of cylindrical nanowire transistors with an arbitrary channel orientation. To perform the subband calculation efficiently, the wavefunctions are expanded using Fourier harmonics. It is confirmed that the use of an approximate isotropic effective mass introduces an error in the subband calculation due to the incorrectly calculated potential energy. A comparison with the results obtained in the Cartesian coordinate system confirms the accuracy of our method. Moreover, the simulation time required to obtain the self-consistent solution is significantly reduced.

© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones. 13 1 1 7

The low-frequency noise behavior of junctionless (JL) gate-all-around (GAA) nanowire (NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It is shown that the predominant 1/f-like noise is governed by carrier number fluctuation (CNF) around threshold voltage operation, while for the p-channel transistors, a pronounced increase in the noise power spectral density is observed at higher gate voltage overdrives. This is due to the impact of the access region to the flicker noise. While the CNF noise is roughly one decade higher for the n-channel than for the p-channel transistors, the opposite holds for the access-related component for both IM and JL GAA NWFETs. It is, finally, observed that the CNF noise is on the average slightly lower in the JL devices compared with their IM counterparts; the origin of this trend will be discussed.

We investigate ultrascaled $\langle 100\rangle $ -, $\langle 110\rangle $ -, and $\langle 111\rangle $ -oriented p-type silicon nanowire transistors using a quantum transport simulator based on the: 1) six-band $\text{k}\cdot \text{p}$ method and 2) sp $^{3}\text{d}^{5}\text{s}^{*}$ tight-binding model. The hole transmission probability from source to drain at low gate voltages shows discrepancies between both models in the $\langle 110\rangle $ and $\langle 111\rangle $ cases. The origin of this phenomenon can be traced back to the nonparabolic band behavior of the imaginary dispersion that is not captured by the six-band $\text{k}\cdot \text{p}$ method. In order to accurately reproduce the full-band (FB) wave function attenuation in the bandgap, the hole energy must be corrected. This approach is validated by comparison with FB calculations. The results suggest that the observed failure of the six-band $\text{k}\cdot \text{p}$ method at ultrashort gate lengths can be avoided, thus extending the applicability of this computationally efficient model.

Sustaining Moore's law requires the design of new materials and the construction of FET. Herein, we investigated theoretically the electronic transport properties of PbSi nanowire Schottky-clamped transistors with a surrounding metal-insulator gate by employing MD simulations and the NEGF method within the extended Hückel frame. The conductance of PbSi nanowire transistors shows ballistic and symmetrical features because of the Schottky contact and the resonance transmission peak, which is gate-controlled. Interestingly, the PbSi(8,17) nanowire FET shows a high ON/OFF ratio and proves to be a typical Schottky contact between atoms as described by the EDD and EDP metrics.

Flexible In2O3 nanowire transistors gated by microporous SiO2-based solid electrolytes are fabricated on paper substrates at room temperature. Low-voltage (1.0 V) operation of these devices is realized owing to the large electric-double-layer capacitance of (1.73 μF/cm2 at 20 Hz) of the microporous SiO2 solid electrolytes, which were deposited at room temperature. The subthreshold swing, current on/off ratio, and field-effect mobility of the paper-based nanowire transistors are estimated to be 74 mV/decade, 1.7×106, and 218.3 cm2/V·s, respectively. These low-voltage paper-based nanowire transistors show promise for use in portable flexible paper electronics and low-cost portable sensors.

In this work, we have designed and analyzed the performance characteristics of n-type silicon based multi-channel junctionless nanowire transistors (JLNTs) for both single gate and double gate configurations. Numerical simulations using CVT (lambardi) model has been carried out to investigate the effects of different device parameters such as gate insulator dielectric, gate insulator thickness, and separating materials between channels. To illustrate and evaluate the performances, input characteristic curves, transconductance, and Ion/Ioff ratio of the devices have been extracted. It is observed that Ion/Ioff ratio are directly affected by the variation of dielectric and thickness of the gate. Devices having a high-κ dielectric provides steeper characteristics and better Ion/Ioff ratio for both the structures. The value of transconductance is also found to be greater for high-κ dielectric in both configurations with the double gate providing a higher value compared to the single one.

This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.

This paper presents a compact analytical model for the static and dynamic electrical characteristics of Junctionless Nanowire Transistors. The static drain current model formulation is derived from the 2D solution of the Poisson equation with appropriate boundary conditions and long-channel devices, leading to a continuous effective surface potential that accounts for the conduction in partial depletion and accumulation regimes. The long-channel model is modified to account for short-channel effects by using the coupled solution of 3D Laplace equation with the 2D Poisson equation. The substrate bias influence on the drain current is also included in the model formulation. The charges at the device terminals are differentiated with respect to the applied biases leading to an analytical description of the transconductances and transcapacitances. The proposed model is validated using experimental data at different bias conditions and temperatures, showing very good agreement.

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.

We compare the electronic characteristics of nanowire field-effect transistors made using single pure wurtzite and pure zincblende InAs nanowires with nominally identical diameter. We compare the transfer characteristics and field-effect mobility versus temperature for these devices to better understand how differences in InAs phase govern the electronic properties of nanowire transistors.

The paper presents a basis expansion scheme for atomistic transport simulations in nanowire MOSFETs. Two simple methods are formulated to calculate current carrying states using a low-dimensional device Hamiltonian in the scattering basis representation. The proposed methods are computationally very cheap and their utility is confirmed by test self-consistent calculations in a p-Si nanowire device.

Research on nanoscale semiconductor devices will elicit a novel understanding of biological systems. First, we discuss why it is necessary to build interfaces between cells and semiconductor nanoelectronics. Second, we describe some recent molecular biophysics studies with nanowire field effect transistor sensors. Third, we present the use of nanowire transistors as electrical recording devices that can be integrated into synthetic tissues and targeted intra- or extracellularly to study single cells. Lastly, we discuss future directions and challenges in further developing this area of research, which will advance biology and medicine.

If nanowire transistors are to be applied to next-generation electronic devices, controlling their characteristics is crucial. In particular, the threshold voltage (Vth) must be controlled because it determines the driving voltage of the transistors. In this research, we were able to control the Vth characteristics in both the negative and the positive directions by performing H2 and O2 gas treatments at room temperature; this control was achieved because oxygen vacancies on the surfaces of the oxide nanowire channel regions could be controlled with the treatments. The H2 treatment changed Vth in the negative direction with increasing processing time (−0.6 V at 10 min; −0.9 V at 30 min; and −1.4 V at 60 min), whereas the O2 treatment changed Vth in the positive direction regardless of the processing time (+0.73 V at 10 min; +0.85 V at 30 min; +0.84 V at 60 min). This method can be applied to display-pixel and digital-logic circuits, especially those that employ nanowire transistors and require Vth control.

We report the application of the discrete Wigner transport equation to the simulation of gate-all-around junctionless nanowire transistors (JLNWTs). We show that unphysical simulation results are obtained unless we pay attention to the accuracy balancing problem. An empirical criterion based on the subthreshold swing of the JLNWT is proposed for the accuracy balancing. Using this criterion, we investigate the characteristics of JLNWTs with the quantum effect fully considered.

The primary goal of this special issue is, therefore, to compile advances in different aspects of nanowire-based devices including device physics and modeling, device design, characterization techniques, technology, and applications so that this special issue will not only be of great archival value but also attract new researchers into this area for further accelerating the application of nanowires in building cheaper and higher performance electronic systems.

Organic nanowires self-assembled from small-molecule semiconductors and conducting polymers have attracted an enormous amount of interest for use in organic field-effect transistors. This new class of materials offers solution processability, the potential for elucidating transport mechanisms and structure-property relationships, and the realization of high-performance transistors that rival the performance of amorphous Si. We discuss the self-assembly of one-dimensional, single-crystalline organic nanowires, show the structures of commonly employed organic semiconductors, and review some of the advances in this field.

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures., 18 pages, 5 figures, In press for Nano Letters (DOI below)

We present a new model for surface roughness (SR) scattering in n-type multi-gate FETs (MuGFETs) and gate-all-around nanowire FETs with fairly arbitrary cross-sections, its implementation in a complete device simulator, and the validation against experimental electron mobility data. The model describes the SR scattering matrix elements as non-linear transformations of interface fluctuations, which strongly influences the root mean square value of the roughness required to reproduce experimental mobility data. Mobility simulations are performed via the deterministic solution of the Boltzmann transport equation for a 1D-electron gas and including the most relevant scattering mechanisms for electronic transport, such as acoustic, polar, and non-polar optical phonon scattering, Coulomb scattering, and SR scattering. Simulation results show the importance of accounting for arbitrary cross-sections and biasing conditions when compared to experimental data. We also discuss how mobility is affected by the shape o...

In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB-EMC transport engine for a 1D electron gas with a 3DPoisson-2DSchro¨dinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the applicability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Green's Functions (NEGFs) in the ballistic limit is used to verify and validate our approach.

Top-down fabrication of sub-50nm silicon nanowire sensors with various geometries.Excellent performance as backgated junctionless nanowire transistors (JNTs).Very good sensing capabilities.Among the smallest top-down fabricated nanowire sensing devices reported to date. This article reports the fabrication of sub-50nm field effect transistor (FET)-type silicon (Si) nanowire (Si NW) chemical and biological sensing devices with a junctionless architecture, as well as on the initial characterisation of their electrical and sensing performance.The devices were fabricated using a fully complementary metal-oxide-semiconductor (CMOS)-compatible top-down process on silicon-on-insulator (SOI) wafers. The fabrication process was mainly based on high-resolution electron beam lithography (EBL) and reactive ion etching (RIE) but also included photolithography (mix-and-match lithography), thin film deposition by electron beam evaporation, lift-off, thermal annealing and wet etching.The sensing performance of a matrix of nanowire devices, i.e. containing 1, 3 and 20 NWs with lengths of 0.5, 1 and 10µm was examined. Each element of the matrix also contained five devices with different NW widths: 10, 20, 30, and 50nm and 5µm (a Si belt reference device). Electrical characterisation of the devices showed excellent performance as backgated junctionless nanowire transistors (JNTs): high on-currents in the range of 1-10µA and high ratios between the on-state and off-state currents (Ion/Ioff) of 6-7 orders of magnitude. In addition, the results of ionic strength sensing experiments demonstrate the very good sensing capabilities of these devices. To the best of our knowledge, these nanowire sensors are among the smallest top-down fabricated Si NW devices reported to date.

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology.

Nanowire transistors are promising candidates for future electronics applications; however, they generally exhibit higher levels of low-frequency noise compared with traditional MOSFETs. The physics of this noise generation in nanowires needs to be understood for improving the device performance. In this paper, the low-frequency noise in InAs nanowire transistors was studied at different gate voltages before and after passivation by a polymethyl methacrylate (PMMA) layer. Noise levels in nanowire devices can be separated into contributions from the channel and from the contacts by analyzing the noise behavior under different bias conditions for devices with varying channel lengths. It is shown that a noise component, which is independent of channel length, can be attributed to the contacts, and a length-dependent component is attributed to the channel. Applying the PMMA passivation layer over the entire device reduces the noise level generated by the channel, but does not change the noise level generated by the contacts. This paper provides a method to understand, and potentially improve, the noise performance. Operation in a channel-dominated bias regime allows extraction of a Hooge parameter specifically for the channel. PMMA passivation was effective in reducing this channel Hooge parameter from 1.4 x 10(-1) to 1.8 x 10(-3).

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.