Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator.

In this paper we present a study of self-heating effects in nanoscale SOI (Silicon-On-Insulator) devices and conventional MOSFETs using an in-house electro-thermal particle-based device simulator. We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional (2D) and the three-dimensional version (3D) of the tool) and then we present a series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in SOI technology. Our simulation results for planar SOI devices (using 2D version of the tool) show that in the smallest devices considered, heat dissipation occurs in the contacts, not in the active channel region of the device. This is because of two factors: pronounced velocity overshoot effect and the smaller thermal resistance of the buried oxide layer. We propose methods in which heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. To simulate self heating in nanowire transistors, the 2D simulator was extended to three spatial dimensions. We study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel in nanowire transistors, the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel. Finally, we examine the importance of self-heating effects in conventional MOSFETs used for low-power applications. We find that the average temperature increase obtained with our simulator of about 10 K is almost identical to the value that has to be used in low-power circuit simulations. [ABSTRACT FROM AUTHOR]