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The use of molecular spin state as a quantum of information for storage, sensing and computing has generated considerable interest in the context of next-generation data storage and communication devices [...]

A physical model is presented for field enhancement (FE) and edge effects of body-tied FinFET charge-trapping NAND flash devices. It is observed that the FE causes a faster speed and a larger memory window, but the effects of nonuniform injection along corner edges complicate the device DC I-V and its programming and erasing characteristics.

The technology status for realizing the gate-all-around nanowire (GAA NW) device structures and their applications in logic circuit and nonvolatile memories are reviewed. The top-down techniques for GAA NW CMOS provide different ways to newer application opportunities for Si technology.

The modeling of a threshold voltage ([V.sub.th]) shift of sub-100-nm NAND Flash memory cell transistors is discussed. Results suggest an accurate prediction of the [V.sub.th] shift of NAND Flash-memory array.

This paper presents a quantitative metric for memory effects in power amplifiers (PAs) and applies it to various active device technologies and wireless system contexts. The proposed metric is mathematically founded in the dynamic two-tone distortion response, has a clear physical meaning in the important field of PA linearization and can be easily evaluated from either harmonic balance simulations or measurement data gathered in a microwave laboratory. In addition, a memoryless PA finearizer, optimum for reducing the integrated intermodulation distortion (IMD) power in the operation bandwidth for a two-tone excitation, is derived, providing a rigorous figure-of-merit of PA linearizability under static IMD compensation. The application of this figure-of-merit is then illustrated for three different PA prototypes based on Si LDMOS, InGaP/GaAs heterojunction bipolar transistors, and GaN high electron-mobility transistors, designed for 900-MHz (global system for mobile communications), 2.1-GHz (wideband code division multiple access), and 3.5-GHz (WiMax) wireless systems, respectively. Index Terms--Long-term memory, memory effects (MEs), non-linear systems, power amplifiers (PAs).

The memory bandwidth reduction for motion estimation is important because of the power consumption and limited memory bandwidth in video coding systems. In this paper, we propose a Level C+ scheme which can fully reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction to save more memory bandwidth compared to the Level C scheme. However, direct implementation of the Level C+ scheme may conflict with some important coding tools and then induces a lower hardware efficiency of video coding systems. Therefore, we propose n-stitched zigzag scan for the Level C+ scheme and discuss two types of 2-stitched zigzag scan for MPEG-4 and H.264 as examples. They can reduce memory bandwidth and solve the conflictions. When the specification is HDTV 720p, where the searching range is [--128,128), the required memory bandwidth is only 54 %, and the increase of on-chip memory size is only 12% compared to those of traditional Level C data reuse scheme. Index Terms--Data reuse, memory bandwidth, motion estimation.

Fullband Monte Carlo simulations and gate current measurements are used to investigate charge injection in split-gate memory cells under negative substrate bias. It is shown that in the source-side-injection (SSI) regime, the enhancement of the programming efficiency due to the substrate bias is low, unless very low drain and floating-gate biases are considered.

The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-[micro]m CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories. Index Terms--Content addressable memory (CAM), dynamic circuits, memory cells, ternary digit (trit) operations, ternary matching.

A study is conducted which applies periodic preventive maintenance to three repair models, major repaired, minimal repaired, or fixed until perfect preventive maintenance upon failure. Two types of preventive maintenance are performed, namely imperfect preventive maintenance, and perfect preventive maintenance.

A simulation of a long-term transient device is performed using a nonvolatile memory cell. It is found that the limitation due to direct tunneling for tunnel oxide thickness is about 3.3-3.4 nm for ten years data retention, whose limitation is not affected by fluctuation due to grain boundaries in the floating-gate (FG) of poly-Si.

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-kappa dielectrics is proposed. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is presented in order to support the importance of work function engineering of the NC in NVM structure.

An energy function-based autoassociative memory design method to store a given set of unipolar binary memory vectors as attractive fixed points of an asynchronous discrete Hopfield network (DHN) is presented. The discrete quadratic energy function whose local minima correspond to the attractive fixed points of the network is constructed via solving a system of linear inequalities derived from the strict local minimality conditions. The weights and the thresholds are then calculated using this energy function. If the inequality system is infeasible, we conclude that no such asynchronous DHN exists, and extend the method to design a discrete piecewise quadratic energy function, which can be minimized by a generalized version of the conventional DHN, also proposed herein. In spite of its computational complexity, computer simulations indicate that the original method performs better than the conventional design methods in the sense that the memory can store, and provide the attractiveness for almost all memory sets whose cardinality is less than or equal to the dimension of its elements. The overall method, together with its extension, guarantees the storage of an arbitrary collection of memory vectors, which are mutually at least two Hamming distances away from each other, in the resulting network. Index Terms--Associative memory, memory storage and retrieval.

In main memory systems, the L2 cache typically employs cache line sizes of 32-128 bytes. These values are relatively small compared to high-dimensional data, e.g., > 32D. The consequence is that existing techniques (on low-dimensional data) that minimize cache misses are no longer effective. In this paper, we present a novel index structure, called [DELTA]-tree, to speed up the high-dimensional query in main memory environment. The [DELTA]-tree is a multilevel structure where each level represents the data space at different dimensionalities: the number of dimensions increases toward the leaf level. The remaining dimensions are obtained using Principal Component Analysis. Each level of the tree serves to prune the search space more efficiently as the lower dimensions can reduce the distance computation and better exploit the small cache line size. Additionally, the top-down clustering scheme can capture the feature of the data set and, hence, reduces the search space. We also propose an extension, called [DELTA]+-tree, that globally clusters the data space and then partitions clusters into small regions. The [DELTA]+-tree can further reduce the computational cost and cache misses. We conducted extensive experiments to evaluate the proposed structures against existing techniques on different kinds of data sets. Our results show that the [DELTA]+-tree is superior in most cases. Index Terms--High-dimensional index, main memory, similarity query.

The study aims on clear, stable mother liquors obtained after completion of crystallization of nanocrystalline sodalite, zeolite A, and zeolite Y. It is observed that during nanocrystalline zeolite synthesis, there are specific primary particles throughout the crystalline process that can grow to form viable nuclei if provided with a source of nutrients.

The physical mechanism of NROM memory erase is investigated. Results reveal that the hot-hole injection will be identified as the actual conduction mechanism of NROM erases, and two compact models capable of describing the main characteristics of NROM, erase current will be developed.

A model is described for modeling defects in the gate oxide of a IT floating gate transistor is described and discussed.

Channel initiated secondary electron (CHISEL) injection programming for NOR Flash electrically erasable programmable read-only memories (EEPROM) is examined and discussed.

A l ow thermal-budget process for fabricating a PZT capacitor is examined and reported.

Silicon (Si) nanocrystal memory is fabricated and characterized.