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Microbiota are communities of diverse microorganisms found in multicellular creatures. The study of microbiota in human bodies initiated since the late of the 19th century, and has been flourishing with the proceeding of the Human Microbiome Project (HMP), an international project aimed to identify the types and roles of the microorganisms in human. So far, human microbiota, especially the microbiota residing in human intestines, have been shown to affect various aspects of human life, including metabolism, immunity, neural activities, aging process, and so on. Some of them are pathogenic, while some of them are beneficial, or even essential to human. In this review, we summarized the up-to-date studies characterizing the influence of different microorganism to human.

In this paper, a novel bridge-type fault current limiter (FCL) based on self-turnoff devices for three-phase power systems is proposed. Compared with the SCR-based bridge type FCL, the new one is smaller in size, better in dynamic performance, and simpler in control method and control circuitry. The novel FCL is composed of a rectifier bridge--a dc-limiting reactor and one/three bypass reactor/reactors--for a single-phase/three-phase structure. The increasing speed of the fault current just after the occurrence of a fault is limited by a dc-limiting reactor, whose inductance is designed according to the response speed of the control circuit. The bypass reactors are designed in terms of the requirements of the coordination of protective relays. The source currents during limiting events are sinusoidal and do not have any harmful effects on the overall protection schemes, impedance relays, and conventional current and voltage transformers. The topologies of the proposed FCL for three-phase four-wire and three-phase three-wire power systems are investigated, respectively, in detail. Parameter design and optimization are presented. The fault and fault-mode judgment method is described briefly. Simulations and experimental results prove the feasibility of the new FCL. Index Terms--Fault current limiters, power electronics, power semiconductor devices, power systems faults.

Single-stage power factor corrector (PFC) ac/dc converter with galvanic isolation is preferable in some industrial applications due to its characteristic of cost-effective and high-power density. However, the transformer used for isolation in such topologies can be easily saturated. In this paper, the generation principle of flux density bias for the transformer involved in the single-stage (SS)-type full-bridge (FB) power factor corrector (PFC) converter is analyzed in detail. The maximum flux density bias during every line period is obtained by recursion. Conventional suppressing strategies of flux density bias are analyzed, and a digital suppressing approach is proposed. A 5 kW SS-FB PFC prototype is built and tested, and the proposed control strategy is implemented by means of a digital signal processor (DSP) board based on the TMS320LF2407A. The feasibility of the proposed approach is well verified through the experimental results. Index Terms--Digital signal processor (DSP), flux density bias, full bridge (FB), power factor correction, single-stage (SS).

This paper studies the relations of space-vector modulation (SVM) and carrier-based pulse-width modulation (PWM) for multilevel inverter. The PWMs' generation of SVM can be achieved by carrier-based PWM scheme, but the modulated wave of SVM is acquired by vectors' calculations and switching-states' selection. Based on different selection of redundant switching-states, there are many types of SVM modulated waves, some of which can function equivalently through proper selection of common-mode injections in the case of carrier-based PWM, the others have more freedoms in switching-states' selection than carrier-based PWM. Selection of more switching-states in SVM is propitious to optimize the output voltage, balance the dc power and so on. Then an improved PWM scheme is proposed based on the modulation waves of three-level SVM, which reserves the main advantages of SVM, and can be achieved easily. Finally, a five-level test circuit is built to verify this PWM scheme. Index Terms--Carrier-based pulse-width modulation (PWM), multilevel inverter, space vector modulation (SVM).

This paper presents a novel circuit realization of the three-level space-vector pulse-width modulation (SVPWM) strategy. A simplified algorithm for the three-level SVPWM is proposed. Due to the geometrical symmetry of six sectors, there exist the close relationships in on time calculations and on time arrangement for switches between them. So it can complete the computation of the three-level SVPWM in one sector. Consequently, compared with the conventional algorithm, the proposed algorithm is more suitable to hardware implementation by greatly reducing computation amount. Based on the simplified algorithm, a three-level SVPWM intellectual property (IP) core has been developed using hardware description language (HDL). The designed IP core can serve as a coprocessor to relieve the DSP or MCU from the intensive computation task of the three-level SVPWM. Simulation and experimental results are given to verify the IP core in a field programmable gate array (FPGA). Index Terms--Field programmable gate array (FPGA), intellectual property (IP), three-level space-vector pulse-width modulation (SVPWM).

This paper presents a new topology named zero-voltage switching (ZVS) resonant reset dual switch forward dc-dc converter, which, compared with resonant reset single switch forward dc-dc converter, maintains the advantage that duty cycle can be more than 50%, at the same time disadvantages of high voltage stress for main switches and low efficiency are overcome. In addition, ZVS is achieved for all switches of the presented topology. Therefore, this proposed topology is very attractive for high voltage input, wide range, and high efficiency applications. In this paper, the operation principle and characteristic of this topology are analyzed in detail. Next, the design consideration is presented. Finally, the advantages mentioned above are verified by experimental results. Index Terms--Zero-voltage switching (ZVS).

In this paper, a short circuit phenomenon when dc-dc modules with self-driven synchronous rectifier (SR) run in parallel is described. Three existing driving schemes are analyzed and compared. A novel driving scheme for SR maintains the performance of SR as a self-driven scheme, while solving the problem of a short circuit when modules run in parallel. In addition, the amplitude of an SR driving voltage can be adjusted by using the proposed scheme. Therefore, the scheme is more attractive in the applications of comparatively high-voltage output. The principle of operation and the characteristics of the scheme are analyzed and verified on a 36-75 V input 1.8-V/60-A output experimental prototype, whose size is 1/4 brick and efficiency is above 90% under rating conditions. Index Terms--In parallel, self-driven scheme, synchronous rectifier (SR).

Paper presents a three-level soft switching LLC series resonant dc/dc converter. Zero-voltage switching (ZVS) is achieved for each main switch without any auxiliary circuit. Voltage stress of each main switch is half of input voltage. Zero-current-switching (ZCS) is achieved for rectifier diodes. Wide input/output range can be achieved under low frequency range because of two-stage resonance. Only one magnetic component is required in this converter. Efficiency is higher in high line input, so this converter is a preferable candidate for power products with the requirement of hold up time. For design convenience, relationship between dc gain and switching frequency, load resistance is deduced. Its open load characteristic and short load characteristic are exposed to provide theory basis for no load operation and over current protection. Design consideration of four dead times is presented to assure that voltage stress for main switches is within half of input voltage and ZVS for each main switch is achieved. Finally the principle of operation and the characteristics of the presented converter are verified on a 500 V-700 V input 54 V/10 A output experimental prototype, whose efficiency reaches 94.7 % under rating condition. Index Terms--Hold-up time, resonant converter, three-level.