Design and implementation of three-level space vector PWM IP core for FPGAs

This paper presents a novel circuit realization of the three-level space-vector pulse-width modulation (SVPWM) strategy. A simplified algorithm for the three-level SVPWM is proposed. Due to the geometrical symmetry of six sectors, there exist the close relationships in on time calculations and on time arrangement for switches between them. So it can complete the computation of the three-level SVPWM in one sector. Consequently, compared with the conventional algorithm, the proposed algorithm is more suitable to hardware implementation by greatly reducing computation amount. Based on the simplified algorithm, a three-level SVPWM intellectual property (IP) core has been developed using hardware description language (HDL). The designed IP core can serve as a coprocessor to relieve the DSP or MCU from the intensive computation task of the three-level SVPWM. Simulation and experimental results are given to verify the IP core in a field programmable gate array (FPGA). Index Terms--Field programmable gate array (FPGA), intellectual property (IP), three-level space-vector pulse-width modulation (SVPWM).