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An epoxy-based solder paste (ESP) is a promising alternative to conventional solder pastes to improve the reliability of fine-pitch electrical joining because the epoxy encapsulates the solder joint. However, development of an appropriate epoxy formulation and investigation of its reaction mechanism with solder powder is challenging. In this study, we demonstrate a newly designed ESP consisting of diglycidyl ether of bisphenol F (DGEBF) resin, Sn-3.0 Ag-0.5 Cu (SAC305) solder powder, and L-glutamic acid (Glu), which is a proteinogenic amino acid for biosynthesis of proteins in living systems. The mechanism of the thermochemical reaction was explored and tentatively proposed, which reveals that the products of the reaction between SAC305 and Glu function as catalysts for the etherification of epoxides and alcohols produced by chemical bonding between DGEBF and Glu, consequently leading to highly crosslinked polymeric networks and an enhancement of impact resistance. Our findings provide further insight into the mechanism of the reaction between various formulations comprising an epoxy, amino acid, and solder powder, and their potential use as ESPs for electrical joining.

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low-temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low-temperature lead-free soldering and bonding processes as a possible alternative for flex-on-flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder-on-pad process with Solder Bump Maker based on Sn58Bi for low-temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of 150 °C using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an 85 °C and 85% reliability test, and an SEM cross-sectional analysis.

The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with 15 µm diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to 20 mA/cm 2 and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with 15 µm diameter were obtained.

Energy Harvesting Devices Research Section, Information & Communications Core Technology Research Laboratory218, Gajeong-ro, Yuseong-gu, Daejeon 305-700, Korea(Received June 10, 2015: Corrected June 17, 2015: Accepted June 19, 2015)Abstract: Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection.A novel solder bumping material (SBM) has been developed for the 60 µm pitch SoP using screen printing process. SBM,which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to performa fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent,and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during thebumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fab-ricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has6724 under bump metallization (UBM) with a 45 µm diameter and 60 µm pitch. The Si chip with Cu pillar bump isflip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfillmaterial is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimizedinterconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is thefirst report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process. Keywords: solder-on-pad, fine pitch bumping, micro bump interconnection

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are , , and , respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than . InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than . A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at .

An electro-plating technology on a cured isotropic conductive pattern with a hybrid Cu paste composed of resin matrix, copper, and solder powders has been developed. In a conventional technology, Ag paste was used to perform a conductive pattern on a PCB or silicon substrate. From previous research, the electrical conductive mechanism and prin- ciple of the hybrid Cu paste were concisely investigated. The isotropic conductive pattern on the PCB substrate was per- formed using screen-printing technology. The optimum electro-plating condition was experimentally determined by processing parameters such as the metal content of the hybrid Cu paste, applied current density, and time for the electro- plating in the plating bath. The surfaces and cross-sections were observed using optical and SEM photographs. In con- clusion, the optimized processing conditions for Cu electro-plating technology on the conductive pattern were a current density of 40mA/cm 2 and a plating time of 20min on the hybrid Cu paste with a metal content of 44 vol.%. More details of the mechanical properties and processing conditions will be investigated in further research.

For the fine-pitch application of flip-chip bonding with semiconductor packaging, fluxing and hybrid underfills were developed. A micro-encapsulated catalyst was adopted to control the chemical reaction at room and processing temperatures. From the experiments with a differential scanning calorimetry and viscometer, the chemical reaction and viscosity changes were quantitatively characterized, and the optimum type and amount of micro-encapsulated catalyst were determined to obtain the best pot life from a commercial viewpoint. It is expected that fluxing and hybrid underfills will be applied to fine-pitch flip-chip bonding processes and be highly reliable.

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-μm diameter and 60-μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μ m, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is successfully formed.

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

As an isotropic conductive adhesive, that is, a hybrid Cu paste composed of Cu powder, solder powder, and a fluxing resin system, has been quantitatively characterized. The mechanism of an electrical connection based on a novel concept of electrical conduction is experimentally characterized using an analysis of a differential scanning calorimeter and scanning electron microscope energydispersive X-ray spectroscopy. The oxide on the metal surface is sufficiently removed with an increase in temperature, and intermetallic compounds between the Cu and melted solder are simultaneously generated, leading to an electrical connection. The reliability of the hybrid Cu paste is experimentally identified and compared with existing Ag paste. As an example of a practical application, the hybrid Cu paste is used for LED packaging, and its electrical and thermal performances are compared with the commercialized Ag paste. In the present research, it is proved that, except the optical function, the electrical and thermal performances are similar to pre-existing Ag paste. The hybrid Cu paste could be used as an isotropic conductive adhesive due to its low production cost.

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip- chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction. 150 µm. The proposed technologies were solder jetting, controlled collapse chip connection new process (C4NP), electro-plating, micro-ball placement, super solder, and so on. Each technology has its own disadvantages, such as expensive equipment, low throughput, and environmental problems. In this letter, we propose a novel bumping material for SoP technology. The basic idea is similar to the solder bump maker (SBM), which is based on the rheological behavior of the solder in resin (3)-(5). However, the major component of the resin in the SBM was epoxy, the solder of which has a low- melting-point, making the SBM inapplicable to the SoP technology. To resolve those problems, we adopted the Sn3Ag0.5Cu (SAC305) solder and developed a new resin which can endure high temperature process so that a cleaning process can be performed after the bumping process. This SBM with SAC solder has the same features as the SBM with low-melting-point solder (3). The characteristics of the resin with and without solder were analyzed using differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). The wetting behavior of SAC305 solder in the resin on Au finish and Cu finish electrodes was observed. Finally, an SAC solder bump array with pitch of 150 µm in one direction was formed using the SBM with SAC, and its morphologies were characterized.

In this paper, we present the fabrication of 40 Gb/s traveling-wave electroabsorption modulator-integrated laser (TW-EML) modules. A selective area growth method is first employed in 40 Gb/s EML fabrication to simultaneously provide active layers for lasers and modulators. The 3 dB bandwidth of a TW-EML module is measured to be 34 GHz, which is wider than that of a lumped EML module. The 40 Gb/s non-return-to-zero eye diagram shows clear openings with an average output power of +0.5 dBm.

In this letter we present a right-angle-bent coplanar waveguide (CPW) which we developed for the application of the driver amplifier-integrated (DAI) 40 Gbps traveling wave electroabsorption modulated laser module. The developed CPW realized parallel progression of the radio frequency (RF) and light using a dielectric overlay structure and wedge bonding on the bending section. The measured S11 and S21 of the developed CPW were kept below -10 dB up to 35 GHz and -3 dB up to 43 GHz, respectively. These measured results of the CPW were in good agreement with the simulation results and demonstrated the applicability of the CPW to the 40 Gbps communication module.

This letter proposes a new impedance matching scheme of a traveling wave electro-absorption modulator (TWEAM) module for a 60 GHz band radio-over- fiber (ROF) link. A microstrip band pass filter (BPF) was used to achieve impedance matching at the 60 GHz band, and termination resistance was carefully designed to obtain an input impedance close to 50 Ω.. Also, a bias circuit for the device was designed in the module. The measured return loss and frequency response show that the modulator module observes the characteristics of a filter without the need of a further tuning process.

We developed an analog 60-GHz module for RF/optic conversion by using an electroabsorption modulator (EAM) device associated with a traveling-wave electrode. The impedance matching of the module was accomplished with the 30-/spl Omega/ termination such that the resonance was precisely located at 60 GHz and the fractional bandwidth at S/sub 11/=-15 dB was as large as 1.0 GHz. The RF/optic conversion gain of the EAM device revealed a strong dependence on the input optical power and was closely related with the slope change in the optical transmission characteristic with reverse bias. From the EAM module with the composite-type multiple-quantum-well electroabsorption core consisting of both 8- and 12-nm quantum wells, we obtained the optimal RF/optic conversion gain at the reverse bias between 1.5-2 V in a wide range of input optical power from -6 to +9 dBm. In the same bias range, the third-order intermodulation distortion was

We fabricated 40 Gb/s front-end optical receivers using spot-size converter integrated waveguide photodiodes (SSC-WGPDs). The fabricated SSC-WGPD chips showed a high responsivity of approximately 0.8 A/W and a 3 dB bandwidth of approximately 40 GHz. A selective wetetching method was first adopted to realize the required width and depth of a tapered waveguide. Two types of electrical pre-amplifier chips were used in our study. One has higher gain and the other has a broader bandwidth. The 3 dB bandwidths of the higher gain and broader bandwidth modules were about 32 and 42 GHz, respectively. Clear 40 Gb/s non-return-to-zero (NRZ) eye diagrams showed good system applicability of these modules.

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an S 1 1 of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

Reaction characteristics of the In-15Pb-5Ag (wt.%) solder with a Au/Ni/Cu pad during reflow soldering and aging treatment were examined. Interfacial reaction during reflow resulted in either an AuIn2 or Ni28In72 layer, depending on reflow time. The AuIn2 layer became thinner and disappeared from the interface, and only the Ni28In72 layer grew with the progress of aging treatment at 130°C. Based on those observations, the dissolution rate of the Au top layer was estimated, and the behavior of the AuIn2 layer during reflow and aging treatment was discussed. In addition, peak shear load and fracture energy of the solder bump were measured as a function of reflow time and aging treatment. The results were compared with those measured with the Sn-37Pb solder bump.

A novel, maskless, low-volume bumping material, called solder bump maker, which is composed of a resin and lowmelting-point solder powder, has been developed. The resin features no distinct chemical reactions preventing the rheological coalescence of the solder, a deoxidation of the oxide layer on the solder powder for wetting on the pad at the solder melting point, and no major weight loss caused by outgassing. With these characteristics, the solder was successfully wetted onto a metal pad and formed a uniform solder bump array with pitches of 120 μm and 150 µm.

We present high-sensitivity photoreceivers based on a vertical- illumination-type 100% Ge-on-Si p-i-n photodetectors (PDs), which operate up to 50 Gb/s with high responsivity. A butterfly-packaged photoreceiver using a Ge PD with 3-dB bandwidth (f(-3dB)) of 29 GHz demonstrates the sensitivities of -10.15 dBm for 40 Gb/s data rate and -9.47 dBm for 43 Gb/s data rate, at BER of 10(-12) and λ ~1550 nm. Also a photoreceiver based on a Ge PD with f(-3dB)~19 GHz shows -14.14 dBm sensitivity at 25 Gb/s operation. These results prove the high performance levels of vertical-illumination type Ge PDs ready for practical high-speed network applications.

We propose and demonstrate the use of subcarrier/polarization-interleaved training symbols for channel estimation and synchronization in polarization-division multiplexed (PDM) coherent optical orthogonal frequency-division multiplexed (CO-OFDM) transmission. The principle, the computational efficiency, and the frequency-offset tolerance of the proposed method are described. We show that the use of subcarrier/polarization interleaving doubles the tolerance to the frequency offset between the transmit laser and the receiver’s optical local oscillator as compared to conventional schemes. Using this method, we demonstrate 43-Gb/s PDM CO-OFDM transmission with 16-QAM subcarrier modulation over 5,200-km of ultra-large-area fiber.