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3,067 results on '"Integrated circuits -- Intellectual property"'

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1. From 'Made in China' to 'Created in China': Intellectual Property Rights in the People's Republic of China

2. Patent Issued for Asynchronous ASIC (USPTO 12135580)

3. Researchers Submit Patent Application, 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip', for Approval (USPTO 20240427367)

4. Patent Application Titled 'Throttle Control Circuits For Throttling Activity In Processing Segment Circuits In An Integrated Circuit (Ic) Chip And Related Methods' Published Online (USPTO 20240427368)

5. Patent Application Titled 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240427410)

6. Patent Application Titled 'Method Of Forming Photomask, Layout Pattern And System For Patterning Semiconductor Substrate By Using Photomask' Published Online (USPTO 20240427230)

7. Patent Application Titled 'Integrated Circuits (Ic) Chips Including Throttle Request Accumulate Circuits For Controlling Power Consumed In Processing Circuits And Related Methods' Published Online (USPTO 20240427397)

8. Patent Application Titled 'Broadcasting Power Limiting Management Responses In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240428024)

9. 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427411)

10. 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427369)

11. Researchers Submit Patent Application, '8-T Sram Bitcell For Fpga Programming', for Approval (USPTO 20240428848)

12. Patent Issued for Regression neural network for identifying threshold voltages to be used in reads of flash memory devices (USPTO 12175363)

13. Patent Issued for Processing of ethernet packets at a programmable integrated circuit (USPTO 12174782)

14. Patent Issued for Method for detecting reverse engineering on a processor using an instruction pointer and corresponding integrated circuit (USPTO 12174950)

15. Patent Issued for FPGA-based USB 3.0/3.1 control system (USPTO 12174779)

17. Patent Application Titled 'Receivers And Semiconductor Memory Devices Including The Same' Published Online (USPTO 20240430140)

18. Patent Application Titled 'Decision Feedback Equalization In Semiconductor Devices' Published Online (USPTO 20240428822)

19. 'Traffic Management And Control Method And Apparatus, And Device And Readable Storage Medium' in Patent Application Approval Process (USPTO 20240430210)

20. Patent Issued for Seamlessly integrated microcontroller chip (USPTO 12169464)

21. Patent Issued for Method for external devices accessing computer memory (USPTO 12169647)

24. Patent Issued for Distributed arbitration for shared data path (USPTO 12169466)

25. Patent Application Titled 'Semiconductor Apparatus And Semiconductor System Having Lun Selection Cycle, And Operating Method Of Semiconductor System' Published Online (USPTO 20240419615)

26. Patent Application Titled 'Page Buffer, Semiconductor Device Including The Page Buffer, And Operating Method Of The Semiconductor Device' Published Online (USPTO 20240420768)

27. 'Semiconductor Apparatus And Semiconductor System Having Lun Selection Cycle, And Operating Method Of Semiconductor System' in Patent Application Approval Process (USPTO 20240420743)

28. 'Interface Regions, And Associated Devices And Systems' in Patent Application Approval Process (USPTO 20240420747)

29. Patent Issued for Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip (USPTO 12164147)

30. Researchers Submit Patent Application, 'Signal Integrity Monitoring System', for Approval (USPTO 20240410943)

31. Researchers Submit Patent Application, 'Oscillating Signal Generating Circuit And A Semiconductor Apparatus Using The Same', for Approval (USPTO 20240413814)

32. Patent Issued for Layout method and layout apparatus for integrated circuit (USPTO 12164852)

33. Patent Issued for Integrated circuit having adaptive uart serial interface (USPTO 12164458)

34. Patent Issued for Hardware autoloader (USPTO 12164637)

35. Patent Application Titled 'Wafer With Micro Integrated Circuits' Published Online (USPTO 20240413133)

36. 'Embedded Memory Device, Integrated Circuit Having The Same And Method Of Operating The Same' in Patent Application Approval Process (USPTO 20240412771)

37. Patent Issued for Compute device housing with layers of electromagnetic interference shields, and devices and systems for the same (USPTO 12158783)

38. Researchers Submit Patent Application, 'Tamper Detector Based On Power Network Electrical Characteristic', for Approval (USPTO 20240403495)

39. Researchers Submit Patent Application, 'On-Chip (In-System) Triggering Of Logic Analyzer', for Approval (USPTO 20240403193)

40. Patent Issued for Three-dimensional integrated system of RFID chip and super capacitor and preparation method thereof (USPTO 12159179)

41. Patent Issued for Monitoring circuit, integrated circuit including the same, and operating method of monitoring circuit (USPTO 12158501)

42. Patent Issued for High-speed, low distortion receiver circuit (USPTO 12160204)

43. Patent Application Titled 'Package And Integrated Circuit With Interface Detection' Published Online (USPTO 20240403256)

44. Patent Application Titled 'Integrated Circuit' Published Online (USPTO 20240403252)

45. Patent Application Titled 'Integrated Circuit Design Methodology Using Phantom Design Without Physical View' Published Online (USPTO 20240403535)

46. 'Wavelength Variable Laser' in Patent Application Approval Process (USPTO 20240405512)

48. Researchers Submit Patent Application, 'Random Function Selection And Insertion During Compilation For Post-Silicon Validation', for Approval (USPTO 20240393395)

49. Patent Issued for Forming nanosheet transistor using sacrificial spacer and inner spacers (USPTO 12154971)

50. Researchers Submit Patent Application, 'Thermal Management Module Of An Integrated Circuit Assembly', for Approval (USPTO 20240395660)

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