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A short-circuit detection (SCD) circuit is proposed for power electronics systems that use silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( MOSFET s). The proposed SCD circuit incorporates a digital circuit for processing the voltage induced at the parasitic inductance of the source of SiC MOSFET to obtain an improved stable turn- off operation of the SiC MOSFET under SC condition. Compared with that of the conventional analog signal processing based SCD circuits, the proposed circuit has the advantages of having a turn- off operation which is robust to process, voltage, and temperature variations, being fully integrated without the use of external components and ease of design. The proposed circuit was implemented in a 350-nm Bipolar-CMOS-DMOS process. For functional verification, an SC test board integrating the proposed SCD circuit was developed. Experimental result validates that the proposed SCD circuit effectively functions under SC condition.

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves −35.8 dBm in-band input-referred third-order intercept point (IIP3), > −22.3 dBm out-of-band IIP3, and an average 3rd LO HRR of 43 dB over 300–800 MHz in DBM&HR mode. Over 600–1200 MHz in SHM mode, it shows >31.8 dB conversion gain, −30.9 dBm in-band IIP3, and > −20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.

This paper presents a highly efficient InGaP/GaAs HBT power amplifier (PA) implemented using a proposed high- $Q$ single- and two-winding transformer. A single- and two-winding transformer is designed with a printed circuit board (PCB) to combine the output power with a reduced passive loss. Compared to a typical 1:2 two-winding transformer, an additional unit amplifier is connected at the mid-point of the secondary winding to construct a single-winding transformer without additional windings. An IMD3 cancellation technique using a single- and two-winding transformer is also proposed to obtain a high linear output power with high power-added efficiency (PAE) without additional design circuitry. The IMD3 components of the two input currents in the single- and two-winding transformer are 180° out-of-phase cancelling each other at output. The proposed PA is integrated with an InGaP/GaAs HBT process using a PCB transformer. The experimental results demonstrate that the PA achieves a saturated output power of 33.3 dBm, with a PAE of 61.3% at 0.91 GHz. The proposed PA is also tested with an orthogonal frequency-division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signal having a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB at 0.91 GHz to evaluate the improvement in linearity. The PA achieves an adjacent channel leakage ratio (ACLR) of −42 dBc up to an output power of 26.0 dBm with a PAE of 26.8% and current consumption of 297 mA.

A dual mode InGaP/GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) using a parallel power-combining transformer (PCT) is presented herein. A low loss transformer is implemented on a printed circuit board (PCB) to improve the passive efficiency of a PCT. Dual-mode operation is applied to reduce the current consumption at a low power level. In the low-power (LP) mode, one of the individual amplifiers is turned off to reduce the current consumption. Additionally, a third-order intermodulation distortion (IMD3) cancellation method using a PCT combiner is proposed to improve linearity performance. Nonlinear IMD3 components from each amplifier cancel each other out through magnetic coupling in the secondary winding of the PCT. The implemented PA achieves a saturated output power of 33.8 dBm and a peak power-added efficiency (PAE) of 54.5% at 0.91 GHz with a 5-V power supply. An average output power of 25.2 dBm with an adjacent channel leakage ratio (ACLR) of −42 dBc is delivered when the PA is tested with an orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulated (64-QAM) signal with a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB. When compared with the high-power (HP) mode operation, the LP mode operation could save 48% of the current consumption at an average output power of 10.4 dBm.

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1–19.2/18.6–18.8 dBm in the respective ranges of 2.4–2.5/4.9–5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors’ knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9–5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far.

A 24-GHz direct-conversion transmitter is proposed for in-cabin radar applications. The proposed RF transmitter consists of an I/Q up-conversion mixer, an I/Q local (LO) oscillator generator, and a power amplifier. To improve the linearity of the I/Q up-conversion mixer, an inverter transconductor with third-order intermodulation (IM3) distortion cancellation is proposed. To improve the I/Q balancing performance of the I/Q LO generator, a poly-phase filter, including parasitic line inductance, is proposed. By employing a highly linear I/Q up-conversion mixer and a balanced I/Q LO generator, the 24-GHz direct-conversion transmitter achieves high linearity and I/Q balancing characteristics. It is fabricated in a 65-nm CMOS process and consumes 150 mW. It shows an OP1dB of 8.6 dBm, an LO leakage of &minus, 48 dBc, and an image rejection ratio of &minus, 49 dBc for the entire operating band from 24 GHz to 24.5 GHz.

A 24-GHz RF sensing receiver front-end with improved I/Q balanced LO generator is presented for a surveillance radar system. The proposed RF receiver front-end consists of a low-noise amplifier, an I/Q down-conversion mixer, and an I/Q local oscillator (LO) generator circuit. The proposed design method of a polyphase filter at millimeter-wave frequencies provides improved and balanced I/Q signals in comparison to a conventional polyphase filter. The receiver front-end draws 20-mA current from a 1.2-V supply voltage. The measured return loss of the RF input port is less than -10 dB in the range of 23.9–24.3 GHz. The receiver front-end achieves a conversion gain of 26.8 dB, noise figure (NF) of 5.1 dB, and an input 1-dB compression point (input P1dB) of -19.7 dBm in the 23.9–24.3 GHz range. Gain and phase mismatch between the I- and Q-paths at IF output are less than 0.15 dB and 0.3°, respectively.

An electronic warfare (EW) simulator is presented to investigate and evaluate the tracking performance of radar system under the electronic attack situations. The EW simulator has the input section in which the characteristic parameters of radar threat, radar warning receiver, jammer, electromagnetic wave propagation, and simulation scenario can be set up. During the process of simulation, the simulator displays the situations of simulation such as the received signal and its spectrum, radar scope, and angle tracking scope and also calculates the transient and root-mean-squared tracking errors of the range and angle tracking system of radar. Using the proposed EW simulator, we analyze the effect of concealment according to the noise and signal powers under the noise jamming and also analyze the effect of deception by calculating errors between the desired value and the estimated one under the deceptive jamming. Furthermore, the proposed EW simulator can be used to figure out the feature of radar threats based on the information collected from the EW receiver and also used to carry out the electronic attacks efficiently in electronic warfare.

A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18- $\mu\text{m}$ CMOS process for TV tuner applications. It shows a measured voltage gain $(A_{v})$ of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than −20 dBm in the frequency range from 44 to 880 MHz. The baseband coefficient scaling and summation based on the current mirror ensure a third- and fifth-harmonic rejection ratio of over 45 dBc in measurement with high linearity performance. The power consumption of the proposed TV receiver front-end is 16.2 mW at a 1.8-V supply voltage.

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

A modified series combining transformer incorporating an autotransformer for the dual-mode operation to improve efficiency performance in the low-output power region is presented. The dual-mode CMOS power amplifier (PA) with the proposed reconfigurable transformer is fabricated using 40-nm CMOS technology. Compared with other dual-mode WLAN CMOS PAs, the proposed PA achieves high-efficiency performance in both high-power and low-power modes; in dual-mode operation, the PA has average output power levels of 19.2 and 15.2 dBm with power added efficiencies of 17.3 and 14.4%, respectively, while satisfying the error vector magnitude requirements of WLAN 802.11g signals.

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-mm CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 &micro, m CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than &minus, 30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz.

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a 0.18-mm CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T- DMB, and ISDB-T with a digital demodulator.

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves ?28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

A low noise and highly linear wideband CMOS receiver front-end for digital TV receivers is proposed. The proposed RF front-end comprises a wideband noise canceling common gate low noise amplifier (LNA) with a capacitively cross-coupled current source, a highly linear up-conversion micromixer with third-order intermodulation distortion cancellation, and a highly linear surface acoustic wave (SAW) driver with enhanced loop gain. The RF front-end was fabricated using a 0.13 μm CMOS process and it draws 27 mA from a 1.5 V supply voltage. It achieves a voltage gain of 23 dB, a noise figure of less than 4 dB, an IIP3 of greater than -6.5 dBm, and an IIP2 of greater than 28 dBm across the entire input band from 54 MHz to 882 MHz.

In this paper, a linearization technique for a transconductor using vertical NPN (V-NPN) bipolar junction transistors (BJTs) in a deep n-well CMOS process is proposed to achieve high linearity performance without degrading power efficiency and noise performance. The proposed transconductor consists of a V-NPN BJT pseudodifferential transconductor (PDT) and a V-NPN BJT fully differential transconductor (FDT). The linearity of the proposed transconductor is improved by canceling the negative peak value of gm'' in the FDT with the positive one in the PDT and by making overall gm'' of the proposed transconductor close to zero. To verify the proposed linearization method, an RF amplifier and a first-order Gm-C low-pass filter adopting the proposed transconductor are designed and implemented in a 0.18-μm deep n-well CMOS process. The implemented RF amplifier and Gm-C low-pass filter achieve 5.8- and 8.5-dB improvements over conventional circuits in the output-referred third-order intercept point, respectively.

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 ㎓ LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ㎛ CMOS process and draws 7.3 ㎃ from a 1.2 V supply voltage. It shows a voltage gain of 40 ㏈ and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

The testing of a monolithic bio-signal acquisition circuit with an analogue negative feedback loop for ubiquitous healthcare (u-healthcare) and the monitoring of physical activity is described. The large low-frequency signal is effectively rejected by the proposed circuit, allowing the dynamic range of the more valuable signals to be improved. The proposed circuit has been designed and fabricated using a 0.18 μm 1-poly 6-metal CMOS process. Using an analogue negative feedback loop with a dual-gain filter, the proposed method provides an average signal-to-noise ratio 8.1 dB higher than that of the conventional method.

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-/spl mu/m CMOS process. V-NPN has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP/sub 2/ than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP/sub 2/, and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts.

A new pixel circuit and driving method for large-area, high-luminance active matrix organic light-emitting diode (AMOLED) displays were studied to improve the image quality. The AMOLED display was designed with low-temperature poly-silicon thin film transistors (TFTs), which have good stability but poor uniformity. To overcome the uniformity problem, the proposed pixel circuit compensates for variations in the threshold voltage and the mobility of the driving TFT. The proposed pixel circuit can operate in two compensation modes for high-luminance operation; and the black data insertion was introduced to improve the characteristics of moving images. The pixel circuit was designed for an 11.6″WXGA top-emission AMOLED panel, and its non-uniformity was estimated to be < 4% with a mobility compensation time of 1 μs.

A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 µm CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.

A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.

The proposed RF front-end circuits consist of a low noise amplifier using an on-chip transformer and a downconversion mixer using a parasitic vertical bipolar junction transistor and have been implemented in 0.18 mum deep n-well CMOS process. A gain of 33 dB, an IIP3 of -12 dBm, and a DSB noise figure of 4.5 dB have been achieved while consuming 5 mW from a 1.8 V supply

A Weaver-type ultra-high precision image rejection RF mixer architecture composed of analogue RF and digital IF mixers is proposed, along with the error compensating algorithm for various gain and phase mismatches. A prototype 2.4 GHz image rejection mixer using this technique with an image rejection ratio > 70 dB is demonstrated.