A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 ㎛ CMOS

A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 ㎓ LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ㎛ CMOS process and draws 7.3 ㎃ from a 1.2 V supply voltage. It shows a voltage gain of 40 ㏈ and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.