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2. Nonquasi-static effects in saturated bipolar circuits

Author

Wu, B. S., Chuang, C.T., and Lu, P.F.

Subjects
Bipolar integrated circuits -- Models, Business, Electronics, Electronics and electrical industries
Abstract

A nonquasi-static (NQS) model, responsible for intrinsic carrier propagation delays in B/C and B/E junctions of saturated bipolar circuits, assesses the influence of nonquasi-static affects on bipolar characteristics. Normal mode B/E NQS delay time causes NQS effect during turn-on transition. Elimination of overdrive charges and long inverse mode B/C delay time cause severe NQS effects during turn-off transition.

Published
1994

3. Effect of reverse base current on bipolar and BiCMOS circuits

Author

Pong-fei Lu and Chuang, C.T.

Subjects
Electric currents -- Research, Bipolar integrated circuits -- Research, BiCMOS -- Research, Business, Electronics, Electronics and electrical industries
Abstract

An analysis of reverse base current (RBC) effect on bipolar complementary metal oxide semiconductor (BiCMOS) circuits' switching performance is presented. An increase in the collector doping N(sub C) as a solution to the Kirk effect renders the avalanche-generated RBC in the collector-base junction problematic for bipolar output devices leaving saturation levels. Results show that using a bipolar inverter, an ECL gate and several BiCMOS circuits check the switch from fully turning off and providing a self-sustained state although with undue leakage during standby.

Published
1992

4. Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor

Author

Sigal, L., Warnock, J.D., Curran, B.W., Chan, Y.H., Camporese, P.J., Mayo, M.D., Huott, W.V., Knebel, D.R., Chuang, C.T., Eckhardt, J.P., and Wu, P.T

Subjects
Complementary metal oxide semiconductors -- Usage, Mainframe computers -- Design and construction, Microprocessors -- Design and construction
Abstract

This paper describes the circuit design techniques used for the IBM S/390[R] Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

Published
1997

26. HIGH SPEED BIPOLAR SRAMS - DESIGN CONSIDERATIONS AND ADVANCES.

Author

CHUANG, C.T.

Abstract

This paper reviews the design considerations and recent advances in high speed bipolar static random access memories (SRAMs). The design constraints and limitations of some most commonly used bipolar SRAM cells, including the resistor-loaded Schottky-clamped ECL cell, the pnp-loaded ECL cell, and the cell, are examined. Process modification, device optimization, and circuit innovation to address these constraints and limitations are discussed. The density and performance potential of these cells are projected. [ABSTRACT FROM AUTHOR]

Published
1991
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