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4 results on '"Bronckers, S."'

1. Substrate noise coupling mechanisms in lightly doped CMOS transistors

Author

Bronckers, S., Van der Plas, G., Vandersteen, G., and Rolain, Y.

Subjects
Printed circuit board, Complementary metal oxide semiconductors -- Usage, Noise control -- Methods, Circuit printing -- Design and construction, Printed circuits -- Design and construction, Semiconductor doping -- Analysis
Published
2010

2. A methodology to predict the impact of substrate noise in analog/RF systems

Author

Bronckers, S., Scheir, K., Van der Plas, G., Vandersteen, G., and Rolain, Y.

Subjects
Standard IC, Complementary metal oxide semiconductors -- Usage, Electromagnetic noise -- Evaluation, Integrated circuits -- Design and construction, Semiconductor chips -- Design and construction
Published
2009

4. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Author

Vladimir Cherman, Steven Thijs, Wouter Ruythooren, Dimitri Linten, Dimitrios Velenis, I. De Wolf, J. Van Olmen, Paresh Limaye, Riet Labie, M. de Potter de ten Broeck, Morin Dehan, V. Simons, Michal Rakowski, Wim Dehaene, Antonio Pullini, Herman Oprins, Igor Loi, Miro Cupac, D. Perry, G. Katti, Marc Nelis, G. Van der Plas, Youssef Travaly, Federico Angiolini, Abdelkarim Mercha, C. Torregiani, N. Minas, Alain Phommahaxay, A. Opdebeeck, Eric Beyne, Rahul Agarwal, Pol Marchal, Michele Stucchi, S Bronckers, B. De Wachter, Luca Benini, Bart Vandevelde, Van der Plas G., Limaye P., Loi I., Mercha A., Oprins H., Torregiani C., Thijs S., Linten D., Stucchi M., Katti G., Velenis D., Cherman V., Vandevelde B., Simons V., De Wolf I., Labie R., Perry D., Bronckers S., Minas N., Cupac M., Ruythooren W., Van Olmen J., Phommahaxay A., de Potter de ten Broeck M., Opdebeeck A., Rakowski M., De Wachter B., Dehan M., Nelis M., Agarwal R., Pullini A., Angiolini F., Benini L., Dehaene W., Travaly Y., Beyne E., and Marchal P.

Subjects
Engineering, business.industry, Circuit design, 3-D, ESD, Integrated circuit design, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, thermal behavior, Circuit reliability, mechanical stre, law.invention, Network on a chip, law, Low-power electronics, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, noise coupling, System on a chip, Signal integrity, Electrical and Electronic Engineering, network-on-chip, CU TSV, business
Abstract

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Published
2011

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