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The impact of thermal post deposition annealing in oxygen at different temperatures on the Ge/Y2O3 interface is investigated using metal oxide semiconductor capacitors, where the yttrium oxide was grown by atomic layer deposition from tris(methylcyclopentadienyl) yttrium and H2O precursors on n-type (100)-Ge substrates. By performing in-situ X-ray photoelectron spectroscopy, the growth of GeO during the first cycles of ALD was proven and interface trap densities just below 1 x 10(11) eV(-1) cm(-2) were achieved by oxygen annealing at high temperatures (550 degrees C-600 degrees C). The good interface quality is most likely driven by the growth of interfacial GeO2 and thermally stabilizing yttrium germanate., QC 20150109

Highly ordered arrays of silicon nanopillars are etched by means of induced-coupled-plasma reactive-ion etching (RIE). The sulfur hexafluoride/oxygen (SF6/O-2)-based cryogenic process allows etching of nanopillars with an aspect ratio higher than 20:1 and diameters down to 30 nm. Diameters can be further reduced by a well-controllable oxidation process in O-2-ambient and a subsequent etching in hydrofluoric acid. This approach effectively removes surface contaminations induced by former RIE, as shown by x-ray photoelectron spectroscopy. Atomic layer deposition (ALD) is used to establish an all-around Al2O3/Pt stack onto the vertically aligned nanorods. Two approaches are successfully applied to remove the resistant Pt coating from the nanopillar tips., QC 20120827

This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed., QC 20130326

The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found., QC 20140912