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Thermally grown SiO2 is widely used for silicon surface passivation in solar cells and other applications due to excellent interfacial properties. SiO2 films with thickness in the range of 17 nm deposited by industrially viable spray-coating technique on both n- and p-type silicon are reported. Low values of interface state density of ${1.4}\times {10}^{{10}}$ cm $^{\boldsymbol -{2}}$ eV $^{\boldsymbol -{1}}$ on n-type and ${2.0}\times {10}^{{10}}$ cm $^{\boldsymbol -{2}}$ eV $^{\boldsymbol -{1}}$ on p-type were achieved. Fixed oxide charges in the range of 7.1– ${9.4}\times {10} ^{{11}}$ cm $^{\boldsymbol -{2}}$ and 3.9– ${6.5}\times {10} ^{{11}}$ cm $^{\boldsymbol -{2}}$ on n- and p-type, respectively, are obtained. Excellent passivation results in the effective surface recombination velocity of 0.97 cms $^{\boldsymbol -{1}}$ and 8.07 cms $^{\boldsymbol -{1}}$ at minority carrier concentration of $10^{{15}}$ cm $^{\boldsymbol -{3}}$ on n- and p-type Czochralski silicon, respectively, without the use of capping layer. SiO2 film exhibits dielectric breakdown field strength of 4.3 MVcm $^{\boldsymbol -{1}}$ and 5.6 MVcm $^{\boldsymbol -{1}}$ and leakage current density of ${2.2}\times 10 ^{\boldsymbol -{8}}$ Acm $^{\boldsymbol -{2}}$ and ${1.1}\times {10} ^{\boldsymbol -{8}}$ Acm $^{\boldsymbol -{2}}$ at 1 MVcm $^{\boldsymbol -{1}}$ on n- and p-type silicon, respectively. These values are superior to sol-gel-based SiO2 films reported previously and are comparable to or better than those reported for other methods for the growth or deposition of SiO2 on silicon. Amorphous nature of the film is validated by high-resolution transmission electron microscopy (TEM). The X-ray photoelectron spectroscopy (XPS) analysis shows nearly stoichiometric SiO x film.

We propose a parasitic BJT-based zero capacitor random access memory (Z-RAM) cell suitable for stand-alone memory applications. In this Z-RAM cell, high-bandgap TiO $$_2$$ is used as the source/drain material and silicon as the channel of an n-channel fully depleted silicon-on-insulator MOSFET. Using well-calibrated TCAD simulations, we demonstrate the programming of the proposed Z-RAM cell at low drain voltages, which is a major advantage from an application perspective. At low drain voltage, hole storage is initiated by band-to-band tunnelling, which is subsequently taken over by impact ionization. Large valence band offset between TiO $$_2$$ and Si ( $$\varDelta { E }_\mathrm{V }\approx$$ 2 eV) is utilized for storing larger number of excess holes inside the body for a longer time. This leads to the improvement of both sense margin and retention time compared to an all-silicon Z-RAM cell. We predict a retention time of 2 s and 70 ms at $$T=300$$ K and 358 K, respectively, for device gate length of 30 nm. We have optimized the device design to obtain a write ‘0’ time of 6 $$\upmu$$ s. Multiple non-destructive reading operation for the proposed Z-RAM cell is also demonstrated.

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells.

The natural soiling of photovoltaic cover glass has recently been shown to include both an inorganic and organic particulate matter. Under favorable growth conditions, the latter can lead to the growth of dense colonies of filamentous fungi, which potentially leads to measurable performance losses over time. Herein, we report on a field study where glass coupon samples were deployed in soiling-prone locations, which focused on Dubai (United Arab Emirates) and Mumbai (India). For each site location, clear differences in the soiling were observed. The samples from Mumbai were contaminated with an abundance of filamentous fungi, whereas the samples from Dubai had primarily inorganic contamination. The effectiveness of soiling mitigation strategies, which include cleaning techniques and glass coatings, are discussed in detail.

Degradation in electrical performance of photovoltaic (PV) modules is related to the degradation of the solar cells and laminate materials in the modules, which often shows up as hot spots in infrared (IR) thermography. The analysis of the IR data of crystalline silicon modules inspected in the field during the All India Survey of Photovoltaic Module Reliability in 2016 is being presented in this paper, along with its correlation to the electrical degradation in these modules. The thermal mismatch in the PV modules has been quantified in terms of a Thermal Mismatch Index, based on the difference between the highest cell temperature and the representative module temperature. Modules with high thermal mismatch (hot cells) under MPPT condition show high power degradation, caused mainly due to fill factor degradation. Modules with hot cells show higher degradation in "Hot" climatic zones as compared with " Non-Hot" climates. The analysis indicates that modules having cracks and hot cells have higher power degradation than modules having cracks but no hot cells. This indicates that the worst cracks tend to create hot cells in the modules, while the benign cracks (which have lesser impact on power output) do not affect the cell temperature to that extent.

Evidence of Poole–Frenkel (PF) transport in vapor–liquid–solid (VLS) grown silicon nanowires is presented. Silicon nanowires were grown in a spherical cold wall catalytic chemical vapor deposition chamber using gold as a catalyst for the VLS growth process. PF transport could be a manifestation of the presence of gold atoms and clusters inside the nanowires acting as Coulombic traps. The activation energy of the process is determined as 60 meV. We also discuss the scaling behavior of PF conduction process in these nanowires.

In this paper, a solar cell with amorphous silicon (a-Si) passivation that uses transition metal oxides (TMOs) for charge carrier collection has been modeled and analyzed for its performance. Charge carrier selection has been incorporated through selective band alignment provided by NiO and TiO2 TMOs for electrons and holes, respectively. The presence of a-Si interfacial layers for defect passivation prevents carrier loss due to high interface state densities at the Si/TMO interfaces. This structure is a potential candidate for high-efficiency solar cells (> 25%) with a realistic approach towards the solution of high defect density. Optical analysis of the proposed structure has been done to analyze the amount of light entering the silicon and capable of generating electron-hole pairs. The amount of light lost has also been quantified into reflection loss, parasitic absorption, and backmetal absorption. Impact of surface passivation quality and doping of NiO and TiO2 on its performance has been analyzed through the detailed device simulations. This provides a realistic pathway for engineering of passivation quality and doping of metal oxides for improved performance.

The transportation of the photovoltaic (PV) modules involves excessive vibrations and shocks. These dynamic loads can crack the solar cells and glass of the PV modules. The cracks generated in solar cells during the transportation phase may not always have immediate implications on the electrical performance of the PV modules. However, in the long-run, cracks generated during transportation of the modules may propagate during operation in field due to wind load, snow load and thermal stresses. The propagation of cracks may create electrical isolation in the cells of a PV module, which can cause loss of electrical power. Therefore, it is important to minimize the damage in PV modules due to transportation and mechanical handling. In this work, PV modules have been transported in packaging following the industry practices to cover a distance of 270 km with accelerometers attached on several modules. Finite element (FE) modelling has been used to calculate natural frequency of vibration for the assembly of the PV modules by simulating the conditions close to the actual transportation experiment. This study shows that transportation makes the modules vibrate at their natural frequency. The first four natural frequencies of vibration calculated through the FE simulations match well with the peaks observed in the power spectral density profiles experienced by PV modules during transportation. Mode shapes corresponding to the first four natural frequencies have also been visualized to identify the contours with maximum displacement. It is hypothesized that out of all the cells, those falling within the contour of maximum displacement would have higher propensity for damage during the transportation. The results presented here can be useful for PV community to improve the packaging methodology, dimensions and material selection of the photovoltaic modules.

A high efficiency (> $$18\%$$ ) industrial large area crystalline silicon wafer solar cell fabrication process generally requires industrial equipment with large footprint, high capital and running costs. Stricter processing window, continuous monitoring and automated functioning are the reasons for it. However, for any conventional laboratory (lab) it is always difficult to manage these requirements with limited available lab space or insufficient fund and other related resources. In this work, we report a novel way to fabricate high efficiency full area aluminium back surface field monocrystalline silicon wafer solar cells in our lab using low-cost processing with small-footprint fabrication tools for 6 inch pseudo-square industrial wafers. The novelty of our work includes optimization of every fabrication process step, e.g., texturization, emitter diffusion, emitter passivation and anti-reflection coating deposition, edge-isolation, screen printing and co-firing individually. These modifications include tuning of processing tools and processes, utility changes and inclusion of additional process steps. Beaker-based chemical processes, manual diffusion furnace, introduction of low temperature oxidation, low temperature silicon nitride deposition processes, plasma-edge isolation tool, single manual screen printer, single oven drying of metal pastes and co-firing using rapid thermal processing tools were used at our lab. For our cells, actual and active area efficiencies of 18.5 and 19% (measured under AM1.5G 1 Sun condition), respectively, were achieved.

Introduction of diamond-wire-sawing (DWS) technique has resulted in significant cost reduction for silicon (Si) wafering process. Unlike slurry-wire-sawn (SWS) wafers, DWS wafer has fewer, non-uniform and thinner saw damage surface. Acid texturing on such surfaces yield highly reflecting and non-uniform texture formation. An additive-free, low cost, non-metallic, energy efficient acid based texturing scheme, named as NCPRE acid texturing, is demonstrated here for DWS multicrystalline Si wafers. The NCPRE acid texturing process employs specific Hydrofluoric-Nitric acid solution to obtain uniform porous silicon (Por-Si) layer. A total of 672 and 1204 cells were fabricated employing the NCPRE acid texturing and additive based acid texturing processes respectively using inline industrial diffusion tools. An impressive batch efficiency of 18.25% is obtained for the NCPRE textured cells against 18.31% cost intensive additive based textured cells. Reasonably close values of cell efficiency establish NCPRE acid texturing a potential candidate for efficient and low-cost DWS mc-Si wafer texturing process.

Metallization of silicon is important to make electrical contacts. Thus, copper (Cu), nickel (Ni) etc. are deposited on Si by various methods including electrochemical and photo-electrochemical methods. Nature of the electrochemical processes of Si with the electrolytes at relevant potentials decides the success of metallization. Thus, it is important to investigate the interaction of electrolyte with Si at cathodic overpotentials. Therefore, n-type and p-type Si of different doping concentrations are investigated in 1% HF electrolyte at cathodic overpotentials. Hydrogen evolution reaction (HER) is expected at very high cathodic overpotentials but very interesting processes occur at intermediate overpotentials. Therefore, the Si/electrolyte interface is investigated using voltammetry (CV), electrochemical impedance spectroscopy (EIS) and Mott-Schottky (MS) analysis. At very high concentration of the dopants, metal-like features are observed with Si. There are very good correlations between dopant concentration, overpotentials, and flat -band potential and inductive behavior of the semi-conductor. Figure. EIS recorded on n-Si at different cathodic overpotentials in 1% HF (a) 4-7 Ωcm (b) 0.00-0.005 Ωcm. The corresponding Bode plots are shown in (d) and (f), respectively. Figure 1

Exposing a plasma-enhanced chemical vapor deposition-deposited silicon nitride (SiN $_{x}$ ) film to an inert gas-oxidizing plasma ambient results in a significant reduction in background plating in the case of electroplated Ni–Cu metallization on c-Si solar cells. However, plasma treatment of SiN $_{x}$ is known to result in a degradation of the Si–SiN $_{x}$ interface. In this paper, we investigate the impact of an Ar/N $_{2}$ O plasma treatment process on the surface passivation properties of SiN $_{x}$ film. Following the plasma treatment, effective minority carrier lifetime ( $\tau _{{\rm eff}}$ ) is seen to improve from 266 to 864 $\mu$ s at a minority carrier density of 10 $^{15}$ cm $^{-3}$ . The interface-state density (D $_{it}$ ) at the Si–SiN $_{x}$ interface also decreases by an order of magnitude, following the Ar/N $_{2}$ O plasma treatment. Enhancement in $\tau _{{\rm eff}}$ is found to be stable for annealing temperatures up to 450 $^{\circ }$ C, which is typically used for Ni–Cu contact sintering. Substrate annealing during the post-deposition plasma treatment process is seen to play a major role in improving the $\tau _{{\rm eff}}$ . Coupled with its potential for reducing the background plating, the proposed process is a promising candidate for developing the passivation layers for cell technologies with low-temperature metallization schemes.

In this study, the impact of impurities incorporated into plated nickel seed layer on silicide formation and the influence of annealing temperature on the fill-factor (FF) loss of solar cells with Ni-Cu contacts is investigated. The silicide growth of electro-less plated nickel seed layer is significantly retarded compared with literature data on physical-vapor-deposition (PVD)-based nickel annealed at 550 degrees C. X-ray photoelectron spectroscopy and X-ray diffraction reveal the presence of SiO2 at the Ni-Si interface and the formation of nickel phosphides in addition to nickel silicide. The retardation in silicide growth is attributed to the presence of (111) planes after the texturing process and contaminants in the seed layer. Varying the annealing temperature of fabricated cells from 350 degrees C to 425 degrees C led to a decrease in the average FF from 79.3% to 77.5%. The loss analysis is based on Suns-V-oc measurements, illuminated current-voltage parameters, and dark current-voltage curve fitting based on a three-diode model. It reveals that the FF loss is dominated by increased junction recombination, whereas losses due to third-diode component become significant for annealing at 400 degrees C and higher temperatures. The results highlight the need to carefully tune the seed layer annealing parameters to the interface conditions and junction depth of solar cells.

We have demonstrated a novel process for the fabrication of inverted pyramidal structures on silicon. The proposed technique uses no photolithography step and is instead replaced by a thin-film deposition step and thermal annealing. In this paper, inductively coupled plasma CVD (ICP-CVD) silicon nitride was used as the thin film. Blisters were formed on the silicon nitride film upon annealing at 800 $^{\circ}$ C. The silicon nitride film remaining on the surface of the wafer acts as an etch mask for the texturization process, which is carried out in an alkaline solution. It was observed that only open blisters participated in the etch process, while closed blisters were resistant to the etching solution. It was observed that the gas flow ratio, annealing time, and temperature played an important role in determining the shape, size, and areal density of the blisters. By integrating an argon plasma pretreatment in the silicon nitride deposition process, surface coverage of 51% was obtained for lower annealing temperatures of 550 $^{\circ}$ C. Upon etching the sample in an alkaline solution, a weighted average reflectance of 17.3% was obtained, indicating the potential of this process.

The All India Survey of Photovoltaic Module Reliability 2014 is an enhanced version of the survey conducted in the previous year, with detailed characterization of PV modules including current-voltage, infrared and electroluminescence imaging, visual inspection, insulation resistance test and interconnect breakage test. More than a thousand modules were inspected in the field and the main results of the survey are presented in this paper. The average Pmax degradation rate for the so-called ‘good’ modules (Group X) is 1.33%/year which is higher than that commonly projected by manufacturers, and widely employed in financial calculations. Modules falling in the ‘not-so-good’ category (Group Y) show even higher degradation rates, and it is at least partly due to higher number of micro-cracks in the modules, and increased degradation of the packaging materials like encapsulant, backsheet, etc. Modules in ‘Hot’ climates degrade faster than modules in the ‘Non-Hot’ climates. Degradation in fill factor is the primary cause for performance degradation in the young modules (ages

This paper presents the analysis of visual degradation data collected during an All-India Survey of Photovoltaic Mod- ule Degradation conducted in 2013, in which 57 crystalline silicon modules were inspected in the five different climatic zones of In- dia. Analysis of the data indicates that the highest percentage of modules suffered discoloration in the Hot and Dry climatic zone, with the Hot and Humid zone coming in second in the list. A higher percentage of modules have suffered corrosion in the Hot and Hu- mid zone, as compared with other zones. The modules installed in the Cold climate suffered the least degradation. Both discoloration and corrosion have been seen in modules across all age groups, even in some of the modules installed less than five years ago. On the other hand, delamination and backsheet degradation have been seen only in modules more than a decade old. The visual degrada- tion data have been correlated with the electrical performance data and reaffirm the direct relation between encapsulant discoloration and reduction in short-circuit current and output power, as well as that of series resistance with metal corrosion.

Work function (WF) tuning of the contact electrodes is a key requirement in several device technologies, including organic photovoltaics (OPVs), organic light-emitting diodes (OLEDs), and complementary metal oxide semiconductor (CMOS) transistors. Here, we demonstrate that the WF of the gate electrode in an MOS structure can be modulated from 4.35 eV (n-type metal) to 5.28 eV (p-type metal) by sandwiching different thicknesses of reduced graphene oxide (rGO) layers between top contact metals and gate dielectric SiO2. The WF of the gate electrode shows strong dependence on the rGO thickness and is seen to be nearly independent of the contact metals used. The observed WF modulation is attributed to the different amounts of oxygen concentrations in different thicknesses of rGO layers. Importantly, this oxygen concentration can also be varied by the reduction extent of the graphene oxide as experimentally demonstrated. The results are verified by X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy analyses. The obtained WF values are thermally stable up to 800 degrees C. At further high temperatures, diffusion of metal through the rGO sheets is the main cause for WF instability, as confirmed by cross-sectional high-resolution transmission electron microscopy analysis. These findings are not limited to MOS devices, and the WF modulation technique has the potential for applications in other technologies such as OLEDs and OPVs involving graphene as conducting electrodes.

Low temperature oxidation of silicon in plasma ambient is a potential candidate for replacing thermally grown SiO2 films for surface passivation of crystalline silicon solar cells. In this work, we report the growth of silicon oxy-nitride (SiOxNy) film in N2O plasma ambient at 380 degrees C. However, this process results in trapping of interstitial oxygen within silicon. The impact of this trapped interstitial oxygen on the surface passivation quality is investigated. The interstitial oxygen trapped in silicon was seen to decrease for larger SiOxNy film thickness. Effective minority carrier lifetime (tau(eff)) measurements on n-type float zone silicon wafers passivated by SiOxNy/silicon nitride (SiNv:H) stack showed a decrease in seff from 347 mu s to 68 mu s, for larger SiOxNy film thickness due to degradation in interface properties. From high frequency capacitance-voltage measurements, it was concluded that the surface passivation quality was governed by the interface parameters (fixed charge density and interface state density). High temperature firing of the SiOxNy/SiNv:H stack resulted in a severe degradation in tau(eff) due to migration of oxygen across the interface into silicon. However, on using the SiOxNy/SiNv:H stack for emitter surface passivation in screen printed p-type Si solar cells, an improvement in short wavelength response was observed in comparison to the passivation by SiNv:H alone, indicating an improvement in emitter surface passivation quality. (C) 2016 AIP Publishing LLC.

In this paper we demonstrate that an additional nitrous oxide (N2O) plasma treatment step after the regular SiNx:H anti-reflective coating (ARC) deposition practically eliminates background plating during Ni-Cu contact metallization for c-Si solar cells. This step is relatively simple and could henceforth enable the commercialization of plated Ni-Cu contacts, which is currently inhibited by the creation of localized metal-silicon interfaces due to background plating, among other issues like adhesion. The average active area efficiency and fill-factor of reference cells without any plasma treatment are 17.4% and 73.5%, respectively. N2O plasma treatment before ARC deposition leads to an improved average fill-factor of 75.0%. This improvement is attributed to a reduction in the area affected by background plating by approximately 40% due to the formation of a thin silicon oxy-nitride layer. N2O plasma treatment after ARC deposition is even more effective and can overcome background plating with an average active area cell efficiency and fill-factor of 18.5% and 77.5%, respectively. This performance improvement is attributed to oxidation of the ARC surface by the plasma post-treatment. Analysis of background plating losses is complemented by current-voltage curve fits to a 3-diode model with resistance limited recombination, performed by the freely available program "2/3-Diode Fit". (C) 2015 Elsevier B.V. All rights reserved.

Evaluation of soiling loss on photovoltaic (PV) modules in a geographical location involves collecting data from a fielded PV system of that location. This is usually a time-consuming and expensive undertaking. Hence, we propose collecting dust samples from various location of interest, preferably from the module surface, and use them as dust samples so that the soiling experiments can be conducted in the laboratory. In this work, a low-cost artificial dust deposition technique is utilized that could be used to deposit dust on a module surface in a controlled manner, which helps in predicting soiling loss associated with various dust properties, including densities, chemical compositions, and particle sizes. The soil samples covering diverse climatic conditions and six different geographic locations covering all of India were collected and investigated. Soiling loss on a silicon solar cell with Mumbai dust (17.1%) is about two times that of Jodhpur dust (9.8%) for the same soil gravimetric density of 3 g/m(2). The dust collected from Mumbai showed the highest spectral loss, followed by Pondicherry, Agra, Hanle, Jodhpur, and Gurgaon. The worst affected module technology was amorphous silicon (17.7%), followed by cadmium telluride (15.7%), crystalline silicon (15.4%), and CIGS (14.5%) for the same density (1.8 g/m(2)) of dust from Mumbai.

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is fully depleted in the OFF state, results in a significant band overlap between the channel and drain regions. This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs. This BTBT leads to a nonnegligible increase in the OFF-state leakage current, which needs to be understood and alleviated. In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential. This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the OFF state. Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT. We present guidelines to optimize the device for high ON-to-OFF current ratio. Finally, we compare the OFF-state leakage of bulk JLTs with that of silicon-on-insulator JLTs.

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope.

Spectral and angle of incidence (AOI) losses on naturally soiled crystalline silicon photovoltaic (PV) modules have been investigated in this study. The test modules designated as "moderately soiled (3 g/m(2))" and " heavily soiled (74.6 g/m(2))" showed short-circuit current (I-sc) losses of about 10% and 41%, respectively. The spectral reflectance and quantum efficiency (QE) losses were also quantitatively determined. In the wavelength range of 350-1100 nm, the average reflectance of moderately and heavily soiled modules increased (as compared with the clean surface) by 58.4% and 87.2%, respectively. In the moderately soiled module, the 26.3% (average) reduction in QE is mainly because of 23% of absorption and 5.5% of reflection in the dust. In the highly soiled module, the 75.3% (average) reduction in QE is mainly because of 62% of absorption and 31% of reflection in the dust particles. It is also seen that the typical critical AOI of 57 degrees for cleaned PV modules decreased to 38 degrees for the moderately soiled module and 20 degrees for the heavily soiled module. This influence is crucial for fixed tilt modules as they experience a wide range of AOI during daily operation, and a significant fraction of energy is generated at higher AOIs.

Reduced multilayer graphene (rMLG) is investigated as a charge storage layer (CSL) in conventional floating gate (FG) flash memory structure. A large memory window of 9.4 V at +/- 20-V program/erase and robust 10-years data retention at 150 degrees C is demonstrated. Significant over-erase observed in these memory devices signifies hole storage in the rMLG sheets. Fast programming and clear saturation of the program transients observed with the rMLG CSL memory devices suggest reduced ballistic transport in the plane perpendicular to the graphene. Activation energies for programmed and erased state retention losses are calculated as 1.05 and 1.11 eV, respectively. These observations establish the potential of rMLG sheets as a replacement of conventionally used polycrystalline silicon FG.

This letter investigates the potential of a low-temperature plasma grown silicon oxy-nitride (SiOxNy) film for surface passivation of silicon surfaces. Using Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy, the film composition is studied to identify the process condition for obtaining a smooth Si-SiOxNy interface. D-it in the order of similar to 10(10)eV(-1)cm(-2), is obtained on capping the SiOxNy with a silicon nitride (SiNv:H) film, followed by annealing at 550 degrees C for 2 s. A surface recombination velocity of 50 cm/s is obtained for the SiOxNy-SiNv:H stack when annealed at 400 degrees C for 2 s. The growth of an interfacial SiOxNy prior to SiNv:H deposition is found to improve the thermal stability of the silicon nitride passivation. The stack could be an interesting option with further optimization for surface passivation of n-type surfaces in mono- and multicrystalline silicon solar cells.

In this paper, we report on the surface passivation of crystalline silicon (c-Si) by pulsed-dc (p-dc) reactive-sputtered aluminum oxide (AlOx) films. For the activation of surface passivation, the films were subjected to post deposition annealing (PDA) in different ambients namely N-2, N-2 + O-2, and forming gas (FG) in the temperature range of 420-520 degrees C. The surface passivation was quantified by surface recombination velocity, which was correlated to the interface states at the silicon-dielectric interface and fixed charges in the dielectric. A good quality surface passivation with effective surface recombination velocity S-eff of 41 cm.s(-1) is obtained for PDA in N-2 or N-2 + O-2 gas ambient. PDA in FG ambient at high temperature is found to degrade the passivation. The AlOx film annealed in FG ambient shows poorer thermal stability as compared with films annealed in the other two ambients. A clear path for further improvements in surface passivation quality of p-dc reactive sputter-deposited AlOx is suggested based on cross-sectional transmission electron microscopy and X-ray photoelectron spectroscopy analysis and electrical data.

Energy levels of traps in silicon nitride are determined using a modified trap spectroscopy method, based on filling of traps using electrical stress followed by optical detrapping, in a metal-silicon nitride-silicon structure. Indium tin oxide with 84% transmittance is used as transparent electrode. Photon energy dependent shift in the flat band voltage is used to estimate type and energetic position of the traps. Here, we report detection of two prominent hole trap levels at 0.5 and 1.1 eV above the valance band edge. The study suggests that phonons hardly participate in the detrapping process of holes in Si3N4. (C) 2013 AIP Publishing LLC.

We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with I-ON = 1.1 mu A/mu m at V-DS = 0.5 V and an I-ON/I-OFF ratio of 3.4.10(4) in n-channel operation. We present further suggestions for device improvements.

Poly(dimethylsiloxane) (PDMS) has been used extensively for microfluidic components and as substrates for biological applications. Since the native nature of PDMS is hydrophobic it requires a functionalization step for use in conjunction with aqueous media. Commonly, oxygen plasma treatment is used for the formation of hydrophilic groups on the surface. However, the hydrophilic nature of these surfaces is short lived and the surfaces quickly revert back to their original hydrophobic state. In this work, branched-polyethylenimine (b-PEI) was used for long term modification of plasma treated PDMS surface. Contact angle, X-ray photoelectron spectroscopy (XPS) and Atomic force microscopy (AFM) were used for characterization of the modified surfaces and their stability with time was studied. The results obtained demonstrate that comparatively higher stability, hydrophilic, positively charged surfaces can be obtained after b-PEI treatment. These b-PEI treated PDMS surfaces can be used as fluidic channels for the separation of molecules as well as a substrate for the adherence of bio-molecules or biological cells. .

The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

Graphene with varying number of layers is explored as metal gate electrode in metal oxide semiconductor structure by inserting it between the dielectric (SiO2) and contact metal (TiN) and results are compared with TiN gate electrode. We demonstrate an effective work function tuning of gate electrode upto 0.5 eV by varying the number of graphene layers. Inclusion of even 1-3 layers of graphene results in significantly improved dielectric reliability as measured by breakdown characteristics, charge to breakdown, and interface state density. These improvements are attributed to the impermeability of graphene for TiN and hence reduced metallic contamination in the dielectric. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4726284]

This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p–i–n p-channel tunnel field-effect transistors using extensive device simulations. Three different device architectures are compared. It is shown that depending on the Ge mole fraction in SiGe and the gate voltage, the tunneling could be from the channel to source or within the source only. Due to this, a very careful optimization of the Ge mole fraction is required to achieve optimum performance. It is also shown for the first time that a vertical gate induced source tunneling is present in the devices and that this could be utilized for improving ON state current by increasing the gate–source overlap. Of the three device architectures compared, the structure with SiGe channel and Si source/drain is found to give better ON state current. Gate length scalability is found to be superior for the structure with SiGe source, and Si channel/drain.

not Available.