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Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology ("2.5D" stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traffic regularly. A load balancing strategy balances the traffics on the two network layers and optimizes the resources utilization. In the aforementioned strategy, after detecting congestion in the CPU layer, packets can be moved to the interposer one. It can be concluded that this transferring encounters the bottleneck of the edge portion that is connected to memory blocks. In this paper, we propose a Controlled Load Balancing Mechanism (CLBM) which efficiently controls bottleneck in load balancing methods. As a result, the CLBM selects an appropriate network based on the destination address without comparing latencies of two networks. Moreover, a multicast fault-tolerant ring is introduced to propagate network congestion information. The experimental results showed that, as compared with the absence of load balancing method and traditional load balancing strategy, our CLBM strategy achieves 37.82% and 17.22% average latency improvements and 22.19% and 8.55% average total power with minor overhead. [ABSTRACT FROM AUTHOR]

As the trends driven by Moore’s law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration. [ABSTRACT FROM PUBLISHER]

Silicon interposers enable the integration of multiple stacks of in-package memory to provide higher bandwidth or lower energy for memory accesses. Once the interposer has been paid for, there are new opportunities to exploit the interposer. In this article, the authors exploit the interposer to "disintegrate" a multicore CPU chip into smaller chips that collectively cost less to manufacture than a single large chip. They study the performance-cost tradeoffs of interposer-based, multichip, multicore systems and propose new interposer network-on-chip (NoC) organizations to mitigate the performance challenges while preserving the cost benefits. Although this article focuses on NoC support for disintegrated systems, it paves the way for a range of new research problems in interposer-based disintegrated systems. [ABSTRACT FROM PUBLISHER]

In 2003, the authors predicted that reconfigurable systems would emerge within 10 years. They expected the arrival of a "Holy Grail"' memory component and chip and wafer stacking. These advances did not occur, which meant that field-programmable gate arrays (the key enabler of reconfigurable systems) did not achieve the breakthrough advance that would enable them for mobile applications. Ten years later, there is no Holy Grail memory component, and there's no wafer stacking; chip stacking is emerging. Reconfigurable systems should appear in markets where equipment has access to continuous power, but financial incentives and the lack of a versatile memory component inhibit their emergence in mobile systems. [ABSTRACT FROM PUBLISHER]

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation. [ABSTRACT FROM AUTHOR]

In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity. [ABSTRACT FROM AUTHOR]