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A surface-modified scalable heat sink that can be fabricated by applying silicon microfabrication technology has been proposed in this paper. Theoretical estimation of the heat sink thermal resistance is based on the heat sink with overall size of 1 cm ? 1 cm ? 1 cm, and four kinds of structure with various total number of grooves on the surface of fins have been investigated. Finite element analysis has been conducted by using COMSOL Multiphysics where fluid dynamics and heat transfer are taken into account. As a result, the lowest heat sinks thermal resistance of 6.84?C per Watt is achieved for the structure with a larger fin area (13.1 cm2) and a higher inlet air flow rate (4 m/s), suggesting an optimum fin area depending on the air flow rate.

In this work, we experimentally investigate the impact of electrical stress on the tunability of single hole transport properties within a p-type silicon MOSFET at a temperature of T = 2 K. This is achieved by monitoring Coulomb-blockade from three disorder based quantum dots at the channel-oxide interface, which are known to lack tunability as a result of their stochastic origin. Our findings indicate that when applying gate biases between −4 V and −4.6 V, nearby charge trapping enhances Coulomb-blockade leading to a stronger quantum dot confinement that can be reversed to the initial device condition after performing a thermal cycle reset. Re-applying stress then gives rise to a predictable response from reproducible changes in the quantum dot charging characteristics with consistent charging energy increases of up to ≈50% being observed. We reach a threshold above gate biases of −4.6 V, where the performance and stability become reduced due to device degradation occurring as a product of large-scale trap generation. The results not only suggest stress as an effective technique to enhance and reset charging properties but also offer insight on how standard industrial silicon devices can be harnessed for single charge transport applications.

We show a manipulation of a single electron at room temperature by controlling Random Telegraph Signals (RTSs) by voltage pulses. Our silicon nanowire triple-gate transistor exhibited RTSs when potential barriers were electrically created by two of the three gates. From the statistics of the signals, we optimized the voltage pulse such that a single electron was intentionally captured in the potential well, and the retention time of approximately 10 ms was observed in this memory operation. This study indicates that a single electron effect can be controllable in a form of RTSs at room temperature by electrically defining a potential well.

Surface-exposed uniformly doped silicon-on-insulator channels are fabricated to evaluate the accuracy of Kelvin Probe Force Microscopy (KPFM) measured surface potential and reveals the role of surface charge on the exposed channel operated in the ambient environment. First, the quality of the potential profile probed in the vacuum environment is assessed by the consistency of converted resistivity from KPFM result to the resistivity extracted by the other three methods. Second, in contrast to the simulated and vacuum surface potential profile and image, the ambient surface potential is bent excessively at the terminals of the channel. The excessive bending can be explained by the movement of surface charge under the drive of geometry induced strong local electric field from the channel and results in non-uniform distribution. The dynamic movement of surface charges is proved by the observation of time-dependent potential drift in the ambient measurement. The result suggests the surface charge effect should be taken into account of the measurement of the surface potential in the ambient environment and the design of charge sensitive devices whose surfaces are exposed to air or in ambient conditions in their operation.

The need for hardware random number generators (HRNGs) that can be integrated in a silicon (Si) complementary-metal-oxide-semiconductor (CMOS) platform has become increasingly important in the era of the Internet-of-Things (IoT). Si MOSFETs exhibiting random telegraph signals (RTSs) have been considered as such a candidate for HRNG, though its application has been hindered by RTS's variability and uncontrollable, unpredictable characteristics. In this paper, we report the generation and randomness evaluation of random numbers from RTSs in a Si single electron pump (SEP) device at room temperature. SEP devices are known to consistently produce RTSs due to a quantum dot electrically defined by multi-layer polycrystalline Si gates. Using RTSs observed in our devices, random numbers were extracted by a classifier supported by supervised learning, where part of data was used to train the classifier before it is applied to the rest to generate random numbers. The random numbers generated from RTSs were used as inputs for the Monte Carlo method to calculate the values of π, and the distribution was compared against the result obtained from the Mersenne Twister, a representative pseudo-random number generator (PRNG), under the same condition. π was estimated more than 80 000 times, and the distribution of the estimated values has a central value of 3.14 with a variance of 0.273, which is only twice as large as the result from PRNG. Our result paves a way to fully electronic CMOS compatible HRNGs that can be integrated in a modern system-on-a-chip in IoT devices.

While the importance of atomic-scale features in silicon-based device for quantum application has been recognized and even the placement of a single atom is now feasible, the role of a dopant in the substrate has not attracted much attention in the context of quantum technology. In this paper, we report random telegraph signals (RTSs) originated from trapping and detrapping of an electron by a donor in the substrate of a p-type metal–oxide–semiconductor field-effect-transistor. RTSs, not seen when the substrate was grounded, were observed when a positive bias was applied to the substrate. The comprehensive study on the signals observed reveals that the nature of the RTSs is discrete threshold voltage variations due to the change in the depletion layer width depending on the charge state of a single dopant, neutral or positively charged.

The observation of Random-Telegraph-Noise (RTN) in double-gate Silicon Nanowire transistor at room temperature is reported. The device showing no RTN when the channel is fully inverted exhibits RTN upon application of negative voltage on the double gates forming a Quantum Dot (QD) in the nanowire. The particle nature of an electron explicitly appears in the electron transport characteristic where its wave nature is the dominant mechanism to account for.

Low dimensional strongly correlated electron systems exhibit a variety of exotic phenomena such as fractional quantum Hall effects, high-temperature superconductivity, and topological phase transitions. However, a problem in modern condensed-matter physics is the difficulty to compare theories with experiments, because of the absence of an ideal experimental system whose properties can be controlled in a systematic way. Here we show a state-of-the-art silicon technology can provide a platform to investigate a one-dimensional quantum system, where various theoretical predictions are available on the basis of mathematically rigid models. We have found unusual transport properties in a field-effect-transistor with a wide and short hole-channel under strong electric fields at low temperatures. By gate-induced doping in the transistor, we discovered new current plateaus and negative differential conductances against drain voltages. We have also found anomalous gate leakage currents which increases upon reducing temperatures and reducing the external electric fields. This provides evidence of the broken symmetry of quantum dipoles formed at the gate interface, which increases local electric fields coming from molecular mean-fields. We obtained phase diagrams of the field-induced phase transitions, which will be correlated with a one-dimensional quantum dipole model.

This paper reports novel characteristic features of thermally-passivated Si nanoelectromechanical (NEM) beams fabricated via SOI-CMOS compatible processes with top-down hybrid EB/DUV lithography. Considerable difference of the resonance frequencies between the measurement results of the NEM beams with various lengths and the finite element simulation results suggests that effects of the undercut of the beam supports are serious for sub-micron beams. The resonance frequency of 332.57 MHz observed for an 800-nm-long beam is, to our knowledge, the highest ever as the fundamental resonance mode of lithographically-defined Si NEM beams. Clear change of the temperature dependence of the resonance frequencies with the varied beam lengths, observed for the first time, can be explained by considering effects of thermally-induced strain on the longer beams at higher temperatures.

Display Omitted Suspended narrow conduction channel silicon nanowires fabricated and characterised.Double suspension fabrication employing tailored amorphous silicon sacrificial layer.Low threshold voltage electrical switching with current on/off ratio of 105.In-plane electromechanical pull-in consistent with finite element analysis.Solid technological basis for CMOS compatible low power NEMS switches. Suspended silicon nanowires with narrow (~10nm) conduction channel are fabricated and characterised for further development of low power nano-electro-mechanical (NEM) switching devices using CMOS compatible fabrication. Double suspension fabrication process using an amorphous silicon sacrificial layer and xenon difluoride etching is employed for thermally-oxidised suspended Si nanowire channels. Device current-voltage characteristics demonstrate depletion mode operation of heavy doped nanowires with an on/off ratio of 105 and a threshold voltage of -1.8V. In plane electromechanical pull-in to side gate is demonstrated and confirmed to be consistent with finite element analysis.

We discovered anomalous transport properties in a conventional Si based Metal-Oxide-Semiconductor Field-Effect-Transistor with a wide and narrow hole-channel at low temperatures. We found the quantum dipole formed at the thin gate interface is responsible for the phase transition. We discuss its potential to use for a quantum simulator as a test bed to examine various theoretical concepts in condensed-matter physics.

The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or one hole, and its importance is recognised upon the aggressive scaling. However, the detailed nature of the charge trap remains to be investigated due to the difficulty to find out the exact device, which shows the RTN feature over statistical variations. Here, we show the RTN can be observed from virtually all devices at low temperatures, and provide a methodology to enable a systematic way to identify the bias conditions to observe the RTN. We found that the RTN was observed at the verge of the Coulomb blockade in the stability diagram of a parasitic Single-Hole-Transistor (SHT), and we have successfully identified the locations of the charge traps by measuring the bias dependence of the RTN.

The scaling of Silicon (Si) technology is approaching the physical limit, where various quantum effects such as direct tunnelling and quantum confinement are observed, even at room temperatures. We have measured standard Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (CMOSFETs) with wide and short channels at low temperatures to observe single electron/hole characteristics due to local structural disturbances such as roughness and defects. In fact, we observed Coulomb blockades in sub-threshold regimes of both {\it p}-type and {\it n}-type Si CMOSFETs, showing the presence of quantum dots in the channels. The stability diagrams for the Coulomb blockade were explained by the potential minima due to poly-Si grains. We have also observed sharp current peaks at narrow bias windows at the edges of the Coulomb diamonds, showing resonant tunnelling of single carriers through charge traps.

We have found a systematic way to identify the bias conditions to observe the Random-Telegraph-Noise (RTN) in advanced Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). We measured a p-type MOSFET at 2K, and found narrow bias conditions to observe the RTN presumably caused by charge trapping and de-trapping, which were only observed at low temperatures. It will pave the way to address the nature of a trap, which will be useful to understand the mechanism of RTN to secure the reliability.

The performance of nanoelectromechanical (NEM) resonators is destructively affected by mechanical damping that requires more careful designs of the resonators, along with the improvement of their working environments to be overcome. In this Letter, various sources of damping are studied theoretically for the in-plane clamped-clamped (CC) NEM resonator and compared with the equivalent values for the designed alternative free-free (FF) resonator. The in-plane FF NEM resonator shows higher quality factor compared with its CC counterpart, that is about four orders of magnitude higher for the vacuum- and low temperature-working environments and a six times larger value for the working environment of air and room temperature based on the numerical results. The successful fabrication of the FF NEM resonator proves the feasibility of fabrication for the structure with the presented design. The authors show that by optimising the position of the support beams of the FF NEM resonator, the anchor dissipation, that is, the main restrictive source on the total quality factor for the vacuum- and low temperature-working environments, is minimised to its smallest value.

We have fabricated ultra-narrow (sub-10 nm) short channel (100 nm) silicon (Si) nanowire transistors with atomically flat interfaces based on Si-on-Insulator (SOI) substrates. The raised source and drain electrodes were patterned together with the gate electrode. The smaller threshold voltage in the narrower nanowire suggests self-limiting oxidation during the gate oxide formation.

We investigate local doping concentration modulation of graphene flakes on a SiO2/Si substrate that has been exposed to the same chemicals in device fabrication using tip-enhanced Raman spectroscopy (TERS). By spectral line scanning across the edge of graphene, it is observed that the D peak enhancement is localized in the vicinity of the edge boundary, and the TERS spatial resolution of ~228 nm is obtained. In the TERS spectra significant peak shifts of both the G and 2D peaks are observed more than 7 cm-1 across the hump on graphene within the distance of 1 µm, while both G and 2D peaks are shifted less than 2 cm-1 in the far-field spectra. This indicates that the modulation of hole doping concentration in close proximity on graphene/SiO2/Si can be probed by using TERS surpassing the resolution of a laser diffraction limit of conventional micro Raman spectroscopy.

We present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-?m-long suspended gate, which is a summation of the mechanical pull-in/pull-out times and the tunnel charging/discharging times.

Manipulation of carrier densities at the single electron level is inevitable in modern silicon based transistors to ensure reliable circuit operation with sufficiently low threshold-voltage variations. However, previous methods required statistical analysis to identify devices which exhibit Random Telegraph Signals (RTSs), caused by trapping and de-trapping of a single electron.Here, we show that we can deliberately introduce a RTS in a silicon nanowire transistor, with its probability distribution perfectly controlled by a triple gate.A quantum dot (QD) was electrically defined in a silicon nanowire transistor with the triple gate, and A RTS was observed when two barrier gates were negatively biased to form potential barriers, while the entire nanowire channel was weakly inverted by the top gate.We could successfully derive the energy levels in the QD from the quantum mechanical probability distributions and the average lifetimes of RTSs. This study reveals that we can manipulate individual electron electrically, even at room temperature, and paves the way to use a charged state for quantum technologies in the future.

A silicon three-dimensional photonic crystal (3DPC) structure has been fabricated using a self-aligned, two-directional electrochemical etching method. The spectral component of the photoluminescence (PL) for silicon nanocrystals deposited on the 3DPC structures increase at 750 nm and slightly decrease at 800 nm. Time-resolved PL measurements reveal that the radiative recombination lifetime of the silicon nanocrystals on 3DPC structures decreases at 750 nm and increases at 800 nm compared to those on a silicon substrate without 3DPC structures. We conclude that the spontaneous emission control of silicon nanocrystals has been observed using the 3DPC structures.

We study the electron transport through silicon serial triple quantum dots (TQDs) formed effectively in a lithographically-defined multiple quantum dot system on a silicon-on-insulator substrate at a temperature of 4.2 K. Our serial TQDs are composed of two lithographically-patterned QDs and another one in-between formed by stress during the pattern-dependent oxidation process. The TQDs formation is confirmed by equivalent circuit simulations, which show an excellent agreement with the experimental results. With detailed analysis of the charge configurations in the TQDs, we discuss the distinct properties of the TQDs, including electron transport at the charge quadruple points. In addition, we discuss higher order tunneling processes of the TQDs. The analysis of electron states in the silicon TQDs is a crucial step toward the future implementation of integrated silicon quantum information devices.

We fabricated light emitting diodes (LEDs) using spherically shaped nanocrystalline silicon (nc-Si), which was formed through very high frequency (VHF; 144 MHz) plasma decomposition of SiH4. In addition, we successfully reduced the roughness of the surface and part of the voids separating the dots by finding the adequate annealing conditions. Red electroluminescence was also observed at 12 V with the naked eye at room temperature under forward bias condition. It is suggested that the origin of the electroluminescence (EL) from Si nanocrystals is due to recombination centers in Si nanocrystals by the comparison of EL and photoluminescence spectra.

We demonstrate highly directional etching in silicon 100 nm in diameter with an aspect ratio of 160 with no spiking on the pore walls using magnetic-field-assisted anodization. The relationship between the surface geometry of a silicon electrode and its highly directional etching properties have been investigated. Specifically, we show that the pore shape and pore wall orientation are not determined by the surface pattern but by the etching mechanisms specific to the magnetic-field-assisted anodization. These etching mechanisms enable highly directional and high aspect ratio etching at diameters below 100 nm in scale.

This paper reports on integration of two silicon (Si) charge quantum bits (qubits) and series-connected double single-electron transistors (DSETs) as readout for the first time. We design and fabricate the DSETs composed of double quantum dots (DQDs) connected in series with two side gates patterned on a silicon-on-insulator substrate. The individual SETs are sufficiently sensitive to detect single-charge polarization on the adjacent charge qubits. The fabricated DSETs are characterized at a temperature of 4.2 K by changing the gate voltages applied to the two side gates. The measured Coulomb oscillation characteristics exhibit a clearly defined hexagon pattern, manifesting that the patterned DQDs of the DSETs, indeed, act as interacting charging islands. These results agree very well with the results of equivalent circuit simulation combined with 3-D capacitance simulation. Furthermore, we simulate how single-charge configurations on two charge qubits are sensed with the DSETs by using the measured electrical characteristics for the DSET and the equivalent model. Finally, the scaling-up properties of the proposed system to multiple single-electron transistors (MSETs) are discussed by simulating triple single-electron transistors (TSETs) with triple qubits.

We study the electrostatic coupling in the silicon double quantum dot (DQD) structure as a key building block for a chargebased quantum computer and a quantum cellular automaton (QCA). We realize the three interdot coupling regimes of the DQD structure only by optimizing the DQD design and the thermal oxidation condition. We then demonstrate that the electrostatic coupling between DQDs can be modulated by tuning the negative voltage of the side gate electrode. Note that the interdot coupling was largely modulated with a small decrease in the gate voltage from 0 to � 100 mV because our structure initially has the DQD geometry. Furthermore, the device fabrication is compatible with the conventional silicon complementary metal–oxide–semiconductor (CMOS) process. This structure is suitable for the future integration of CMOS devices. In addition, we show the derivation of the DQDs’ capacitances, including the gate cross capacitances, as a function of the spacing between the two adjacent charge triple points. By using these capacitances, the electron transport properties of the DQD structure are simulated, and the modulation of the electrostatic coupling is successfully simulated as the change of the total capacitance in DQDs. [DOI: 10.1143/JJAP.47.4820]

We report on integration of double nanocrystalline silicon quantum dots (nc-Si QDs) of approximately 10 nm in diameter onto the multiple-gate single-electron transistor (SET) used as a highly-sensitive charge polarization detector. The SET with a single charging island is first patterned lithographically on silicon-on-insulator, and the multiple-gate bias dependence of the Coulomb current oscillation is characterized at 4.2 K. The coupling capacitance parameters between the SET charging island and the multiple-gate are estimated and compared with those obtained by using the three-dimensional capacitance simulation. Double nc-Si QDs are then deposited in the immediate vicinity of the charging island of the SET by using the very-high frequency plasma deposition technique. We perform the single-electron circuit simulations and demonstrate that only ±e charge polarization of the double QDs can be sensed as a shift of the Coulomb oscillation peaks.

We describe a low-temperature millimeter-wave (44 GHz) surface impedance measurement instrument based on the cavity perturbation method. In this instrument, all millimeter-wave paths at low temperatures (including the cavity resonator), are located inside a high vacuum tube, which can be inserted into a 7 T superconducting magnet. This design, which is free of exchange gas, enables measurements over a wide temperature range as well as providing stable and reproducible operation. By pumping a 3He pot attached to a cavity, a sample can be cooled well below 1 K. We present experimental results which demonstrate the performance of the instrument.

We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which co-integrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications.

SiNW synthesis by vapor-liquid-solid (VLS) growth mechanism has been reported by many authors but a deep understanding of the key factors affecting the nanowire growth is still lacking. Here, we report a thorough investigations of the SiNW growth by employing silicon substrates with different crystal orientations and surface preparation using Au thin film as a catalyst. We observed that the activity of the Au particles strongly depends on the crystal orientation and the substrate surface preparation significantly affects the properties of SiNWs. We found that the density and growth rate of nanowires is different in a temperature dependent growth on Si(100) from Si(111). We found that the density and growth rate of nanowires is different at different crystal orientations of the substrates. We have grown nearly uniform diameter and micrometer long SiNWs by using Si 2 H 6 as a source gas in low pressure chemical vapor deposition around eutectic temperature. The length of the SiNWs can be controlled mainly by varying the growth time.

In-plane complex surface impedance of a ${\mathrm{Bi}}_{2}{\mathrm{Sr}}_{2}{\mathrm{CaCu}}_{2}{\mathrm{O}}_{y}$ single crystal was measured in the mixed state at 40.8 GHz. The surface reactance, which is proportional to the real part of the effective penetration depth, increased rapidly just above the first-order vortex-lattice melting transition field and the second magnetization peak field. This increase is ascribed to the decrease in the superfluid density rather than the loss of pinning. This result indicates that the vortex melting transition changes the electronic structure as well as the vortex structure.

Hydrogen silsesquioxane (HSQ) is a high resolution negative-tone electron beam resist allowing for direct transfer of nanostructures into silicon-on-insulator. Using this resist for electron beam lithography, we fabricate high density lithographically defined Silicon double quantum dot (QD) transistors. We show that our approach is compatible with very large scale integration, allowing for parallel fabrication of up to 144 scalable devices. HSQ process optimisation allowed for realisation of reproducible QD dimensions of 50 nm and tunnel junction down to 25 nm. We observed that 80% of the fabricated devices had dimensional variations of less than 5 nm. These are the smallest high density double QD transistors achieved to date. Single electron simulations combined with preliminary electrical characterisations justify the reliability of our device and process.

In this paper we first present a new fabrication process of downscaled graphene nanodevices based on direct milling of graphene using an atomic-size helium ion beam. We address the issue of contamination caused by the electron-beam lithography process to pattern the contact metals prior to the ultrafine milling process in the helium ion microscope (HIM). We then present our recent experimental study of the effects of the helium ion exposure on the carrier transport properties. By varying the time of helium ion bombardment onto a bilayer graphene nanoribbon transistor, the change in the transfer characteristics is investigated along with underlying carrier scattering mechanisms. Finally we study the effects of various single defects introduced into extremely-scaled armchair graphene nanoribbons on the carrier transport properties using ab initio simulation.

In this paper we overview recent attempts at co-integrating silicon nano-electro-mechanical systems (NEMS) with nanoelectronic devices aiming to add more functionalities to conventional electronic devices in ‘More-than-Moore’ domain and also explore novel operating principles in ‘Beyond CMOS’ domain.

Numerical simulation of electromechanical switching for bistable bridges in non-volatile nanoelectromechanical (NEM) memory devices suggests that performance of memory characteristics enhanced by decreasing suspended floating gate length. By conducting a two-dimensional finite element electromechanical simulation combined with a drift-diffusion analysis, we analyze the electromechanical switching operation of miniaturized structures. By shrinking the NEM floating gate length from 1000 to 100 nm, the switching (set/reset) voltage reduces from 7.2 to 2.8 V, switching time from 63 to 4.6 ns, power consumption from 16.9 to 0.13 fJ. This indicates the advantage of fast and low-power memory characteristics.

Single-crystalline ${\text{FeTe}}_{0.61}{\text{Se}}_{0.39}$ with a sharp superconducting transition at ${T}_{c}\ensuremath{\sim}14\text{ }\text{K}$ is synthesized via slow furnace cooling followed by low-temperature annealing. The effect of annealing on the chemical and superconducting inhomogeneities is carefully characterized. We also report resistivity, magnetization, and magneto-optical images of this crystal. Based on the Bean model, critical current density is estimated to exceed $1\ifmmode\times\else\texttimes\fi{}{10}^{5}\text{ }\text{A}/{\text{cm}}^{2}$ below 5 K under zero field. Weak fish-tail effect is identified at lower temperatures.

In this paper we present our recent attempts at developing the advanced information processing devices by integrating nano-electro-mechanical (NEM) structures into conventional silicon nanodevices. Firstly, we show high-speed and nonvolatile NEM memory which features a mechanically-bistable floating gate is integrated onto MOSFETs. Secondly we discuss hybrid systems of single-electron transistors and NEM structures for exploring new switching principles.

We investigate novel serially-connected multiple single-electron transistors (MSETs) as a single-charge polarisation readout for silicon integrated charge qubits. We first design and analyse the double single-electron transistors (DSETs) in which double quantum dots are connected in series with two side gates. We show that the DSETs are sufficiently sensitive to distinguish all the single-charge polarisation states on the two charge qubits integrated adjacently. We also show the scalability of the MSETs by extending our analysis to a scaled-up system of serial triple single-electron transistors (TSETs) integrated with triple charge qubits. Finally we fabricate the DSETs with double charge qubits on the silicon-on-insulator substrate and observe hysteresis in the Coulomb oscillations of the tunnel current at temperature of 4.2 K, which are attributable to the change of polarisation in the double charge qubits.

The SEDs with relatively long constriction regions invariably exhibit the MTJ characteristics due to the dopant induced potential fluctuation. We clarified that the formation of such uncontrolled MTJs can be avoided by making the constrictions extremely short and with low surface roughness.

Double quantum dots (DQDs) have been studied as attractive candidates for charge qubits. Initially, GaAs-based DQDs formed by means of surface gates depletion were studied because many parameters are tunable after their fabrications [1]. However, silicon-based DQDs are more promising for charge qubits because of the absence ofpiezoelectric electron-phonon coupling, and the effect of phonon localization [2]. Furthermore, to integrate Si multiple charge qubits and a readout device in a small footprint, a series-connected double dots transistor has recently been proposed and studied [3]. The readout is called as double single-electron transistors (DSETs) and facilitates to detect the single-charge polarizations on the adjacent double qubits efficiently [4]. The other advantage of DSETs is that both two SETs act as feedback transistors to each other to compensate the random fluctuation noise.

We analyzed the switching and readout properties of the NEMS memory. We found that the damping factor influences highly on the transient response time and is important for the fast operations. By assuming the best damping parameter, the transient response times for the readout operation were found about 20 ns and 90 ns for the ON and OFF states, respectively. And the switching time was about 80 ns for the 7.5 V gate voltage.

Recent advance on fabricating silicon nano electromechanical systems (NEMS) has enabled us to study single-electron tunnelling through nanometerscale suspended structures with restrained coupling to the environment. In particular, a suspended quantum dot cavity structure built on a Si nanobridge provides an ideal system to explore the interaction of single electrons with tailored phonon spectrum in the cavity which is acoustically isolated from the Si substrate. Such a system has recently become of great interest in terms of studying physics of decoherence mechanisms for quantum bits and also revealing ultimate energy dissipation process in Si nanostructures.Here, we report on anomalous suppression of single-electron tunnelling observed for a low source-to-drain region. These characteristics are attributable to the enhanced interaction between tunneling electrons and cavity phonons.

We fabricated the Si MQDADs. and measured their electron transport properties. The currents through the MQDADs were analyzed and the strong interaction. between the two DQDs was observed. The MQDADs are promising candidates for the novel information devices.

Ab initio simulation of 'nanophonons' has been conducted for the first time for the H-terminated ultrathin Si films of 3 to 10 atomic layers in thickness and have revealed that the phonon bandgaps are formed as a result of the Si dimers on the surface.