Search

The effect of controllable process parameters such as metal-gate physical thickness and interfacial-layer-formation method on the electrical and structural properties of TiN/Hf[O.sub.2]/Si[O.sub.2] gate stacks is studied. Hf-rich chemical interfacial oxides have not degraded the device performance and a small reduction in transconductance is seen for physically thinner interfacial layers.

The optimum gate workfunction (GWF) for four-terminal-driven multigate MOSFETs (4T-MUGFETs) is examined. The optimum GWF for the NMOS 4T-MUGFETs is found to be around 4.32eV, whereas 5.17 eV is the optimum GWP for PMOS 4T-MUGFETs.

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

In this paper, we have fabricated high-performance Si0.45Ge0.55 implant-free quantum well (IFQW) pFET with embedded SiGe source/drain stressor. This device showed high drive current of 1.28 mA/ \mu m at I_{\mathrm {\scriptstyle OFF}\_{D}} of 160 nA/ \mu $ m with channel length/width of 30 nm/0.16 $\mu $ m ( $V_{{\rm {DD}}} =-1$ V). Conventional ion-implanted extension is replaced with in situ boron-doped epitaxial Si0.75Ge0.25 layer. This enables lower process temperature which can maintain an integrity of Si0.45Ge0.55 film and thus higher hole mobility. In narrower width devices, we observed significant hole mobility boost ( $1.9\times $ improvement from active width of 10 to $0.1~\mu $ m). This is due to the relaxation of unwanted transverse stress in Si0.45Ge0.55 channel applied from Si substrate. IFQW devices show improved short channel control thanks to the epitaxially formed raised extension structure compared with conventional devices which have implanted extension. Achieved device performance is one of the best among all Si1–xGex-based channel pFET up to date. [ABSTRACT FROM AUTHOR]

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of \Si1-x\Gex\-channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W, the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length LP/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or LP/P is also predicted but only for aggressively scaled layouts (LOD or LP/P below 100 nm). W and LP/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W, LOD, or LP/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels. [ABSTRACT FROM PUBLISHER]

This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]

In this brief, we report on how controllable process parameters such as metal-gate physical thickness and interfacial-layer- formation method affect the electrical and structural properties of TiN/HfO2/SiO2 gate stacks. We found evidence Hf is diffusing into chemically formed SiO2 interfacial layers during device processing. The latter is not seen when SiO2 is formed thermally. We show that the interfacial layer is thinner when the physical thickness of TiN is reduced from 7 to 3 nm, resulting in electrically thinner gate stacks by 2 Å. An electrical thickness in inversion as low as 11.4 Å with gate-leakage-current density equal to 3.5 A/cm2 at 1 V was obtained for spike-annealed thin TiN/HfO2 stacks on chemically grown interfaces. Hf-rich chemical interfacial oxides do not degrade device performance. A small reduction in transconductance is only seen for physically thinner interfacial layers. [ABSTRACT FROM AUTHOR]