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In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra-thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

An inspiring UTBB SOI MOSFET structure with enhanced immunity to the drain-induced barrier lowering (DIBL) is analyzed. The structure includes the dual-gates in the lateral direction. The voltage difference is applied between the dual-gates, through which the electrostatic potential and the energy band along the channel are modified and the electrical performance is boosted. The electrical characteristics are investigated by measuring the electron concentration, the conduction band energy level, and the potential at the front-surface. The impact of the negative voltage bias applied to the right gate on the performance of the new device is studied, and compared to that of the conventional ultra-thin body ultra-thin box silicon-on-insulator (UTBB SOI) devices. The results reveal that the undesirable DIBL values are lower in this innovative device than that in the conventional UTBB SOI MOSFET.

Total ionizing dose (TID) effects in ultra-thin body Ge on Insulator (GOI) junctionless CMOSFETs with recessed source/drain and channel have been studied. 10-keV X-ray irradiation leads to net hole trapping at the top and bottom Ge/dielectric interfaces of both GOI NFETs and PFETs. The Ge channel thickness and post-oxidation processing can strongly affect the radiation response. Application of negative back-gate bias can moderate the radiation-induced threshold-voltage shifts.

This paper reports an ultrahigh-sensitive ISFET sensor that is developed using TCAD model of the industrial 22-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. The modeling method is exploited by changing the potential surface charge depending on the electrolyte pH change and investigating how will it cause the threshold voltage shift of ISFET device and other transfer characteristic parameters. The properties of a user-defined material offered by Silvaco are exploited to simulate the electrolyte behavior. The parameters of silicon semiconductor material (i.e., energy bandgap, permittivity, affinity, and density of states) are set to reconstruct an electrolyte solution. The electrostatic solution of the electrolyte area is investigated by giving a numerical solution for the semiconductor equation inside this area. On the other hand, the strong electrostatic coupling between the front gate and the back gate of FDSOI devices provide an intrinsic signal amplification feature for sensing applications. Utilizing a layer deposited Titanium dioxide (TiO2) as a pH sensing film, pH sensors having a sensitivity ∼1250 mV/pH is reported. The small sensing area and the FDSOI-based technology of the device make the sensors ideal for the IoT market.

This paper investigates the impact of quantum confinement (QC) on the backgate-bias (Vbg) modulated subthreshold and threshold-voltage (Vth) characteristics of ultra-thin-body germanium-on-insulator (UTB GeOI) MOSFETs using an analytical solution of the Schrodinger equation verified with TCAD numerical simulation. Our study indicates that the QC effect reduces the sensitivity of the subthreshold swing to Vbg. In addition, the sensitivity of Vth to Vbg can be enhanced by the QC effect particularly for electrostatically well-behaved UTB MOSFETs with triangular potential well. Aside from that, the sensitivity of Vth roll-off to Vbg is reduced by the QC effect. Since Ge and Si channels exhibit different degrees of QC due to different quantization effective mass, the impact of QC has to be considered when one-to-one comparisons between GeOI and SOI MOSFETs regarding the backgate-bias modulated threshold-voltage and sub-threshold characteristics are made. Our study may provide insights for multi-Vth device/circuit designs using advanced UTB GeOI technologies.

The transfer characteristics of double-gate (DG) MOSFETs are numerically simulated with 2D quantum drift-diffusion (QDD) model. Negative gate-overlap is introduced in devices to optimize the dynamic capacitance characteristics to get the best speed performance. Separate controlling of the back-gate to vary the threshold voltage is investigated, which makes the device convenient to adaptive for more versatile applications, in both high speed and low power dissipation.

In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150–220 GHz. Effect of operation regime, sub- strate bias, channel width and high temperature (up to 250 ° C) on analog figures-of-merit (FoM) are ana- lyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented. Ó

Ytterbium silicide provides a low Schottky barrier height to electron on n-type silicon. This property makes this material very attractive for the realization of Source/Drain contacts for n-type MOSFETs. In this communication, the study of structural and electrical properties of YbSi2-x fabricated at different temperature in Ultra-High Vacuum condition without any protective layers is presented. N-type SB-MOSFETs with ytterbium silicide based S/D contacts were fabricated at optimal silicidation temperatures on SOI substrate with an ultra thin body.

The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm.

This paper discusses a few unique effects of ultra-thin-body double-gate NMOSFET that are arising from the bandstructure of the thin film Si channel. The bandstructure has been calculated using 10-orbital $sp^3d^5s^*$ tight-binding method. A number of intrinsic properties including band gap, density of states, intrinsic carrier concentration and parabolic effective mass have been derived from the calculated bandstructure. The spatial distributions of intrinsic carrier concentration and $ $ effective mass, arising from the wavefunction of different contributing subbands are analyzed. A self-consistent solution of Poisson-Schrodinger coupled equation is obtained taking the full bandstructure into account, which is then applied to an insightful analysis of volume inversion. The spatial distribution of carriers over the channel of a DGFET has been calculated and its effects on effective mass and channel capacitance are discussed.

In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the nonhysteretic operation of NC transistors. We report a clear and significant double improvement in: 1) subthreshold swing and 2) gate overdrive, using the NC effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14-nm node ultrathin body and box fully depleted silicon-on-insulator FET can operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double-gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness. A 14-nm node double-gate negative capacitance FET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.