1. Extension and source/drain design for high-performance finFET devices
- Author
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Ronnen Andrew Roy, Meikei Ieong, J. Kedzierski, Diane C. Boyd, David M. Fried, E.J. Nowak, Thomas S. Kanarsky, Ying Zhang, and Hon-Sum Philip Wong
- Subjects
Fin ,Materials science ,Silicon ,Equivalent series resistance ,business.industry ,chemistry.chemical_element ,Hardware_PERFORMANCEANDRELIABILITY ,Epitaxy ,Electronic, Optical and Magnetic Materials ,Ion implantation ,chemistry ,Gate oxide ,Parasitic element ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Optoelectronics ,Field-effect transistor ,Electrical and Electronic Engineering ,business - Abstract
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.
- Published
- 2003
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