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Extension and source/drain design for high-performance finFET devices

Authors :
Ronnen Andrew Roy
Meikei Ieong
J. Kedzierski
Diane C. Boyd
David M. Fried
E.J. Nowak
Thomas S. Kanarsky
Ying Zhang
Hon-Sum Philip Wong
Source :
IEEE Transactions on Electron Devices. 50:952-958
Publication Year :
2003
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2003.

Abstract

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

Details

ISSN :
00189383
Volume :
50
Database :
OpenAIRE
Journal :
IEEE Transactions on Electron Devices
Accession number :
edsair.doi...........edc5bb393f1aabe145da3751900e783b
Full Text :
https://doi.org/10.1109/ted.2003.811412