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A methodology for fast and accurate estimation of the number and positions of buffers during 3D IC floorplanning is developed. Our algorithm computes candidate buffer positions simultaneously with assignment of 3D nets to TSVs. Through accurate delay characterization of buffered 3D nets, the minimum distance between consecutive buffers is estimated. Additionally, an analytical approach is used to find the optimal position of buffers in front of TSVs. This prevents additional buffers’ insertion around TSVs, incurring lesser delay and power in 3D nets. Experimental results with expanded GSRC benchmarks show 5.6% more reduction in number of buffers, 5.7% reduction in interconnect delay and 4% reduction in dynamic power, compared to a previous published work. The potential impact of nanoscale TSVs on buffer estimation at sub-45 nm technologies is analyzed.

We propose a novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs. We include the non-negligible impact of area occupied by TSVs, perform nets-to-TSVs assignment, and use physical dimensions of TSVs and wires for delay calculations. Our floorplanning is based on co-placement of TSV islands with circuit blocks and is performed under fixed-outline constraints. The total delay is a direct optimization goal in the presented delay-aware 3D floorplanning and accounts for the RC delay impact of TSVs on the delay of each individual net during the nets-to-TSVs assignment. Therefore, compared to traditional wirelength-aware floorplanning, which separately minimize wirelength and the number of TSVs, the proposed approach results in more effective delay minimization. Our experimental results show improved solution quality with up to 9 % shorter wirelength and an average 40 % reduction in the number of TSVs as compared to most recent publications. Total delay reduces between 10 and 12 % when the delay, instead of wirelength and the number of TSVs separately, is minimized.

With a high thermal conductivity of 3000–5000 W/m -K, Graphene outstands almost all materials in effective lateral heat spreading. Will introduction of 2D monolayer graphene in 3D-IC help in vertical heat conduction too? In this work, we investigate the impact of Graphene- and Graphite- -based inter-die thermal interface material (TIM) on the peak temperature of the 3D-IC. We compare configurations of additional intermediate layer (IL) of monolayer graphene, graphite and copper materials along with TIM. Simulations show a peak temperature reduction of up to 50°C in GSRC benchmarks. Role of thermal conductivity and the additional IL critical thickness in peak temperature reduction is also investigated. Our discussion encompasses the vertical thermal profile impact on TSV delay and peak temperature dependence on TIM material, thermal-conductivity and thickness. Lastly, of all configurations, we suggest to further investigate a very promising cost-effective graphite-based inter-die TIM along with graphite-based heat spreaders, to compensate the poor heat dissipation problem in 3D ICs.

This paper characterizes the behaviour of multi-terminal nets in a circuit to provide an accurate estimation of interconnect net-degree distribution. Based on Rent's rule, we derived a new net-degree distribution model, called the weighted exponential model. Numerical evaluations show that weighted exponential model is more accurate than any other currently available net-degree distribution models. It generates from 18% to 87% smaller average absolute errors in the prediction of the total number of nets and average net degree. Moreover, it was observed that the internal fraction factor f, that represents the ratio of the number of new internal nets to the total number of new nets, similarly to Rent's rule, exhibits Regions II and III. With a refined value of f, our model can provide even more accurate estimation of net-degree distribution. A method to generate floorplanning benchmarks using weighted exponential model is presented. Thanks to the accuracy of new model and the introduction of a block-degree distribution, the significantly improved benchmark generator, BGen, outperforms a prototype tool we have previously developed using Zarkesh-Ha et al's model.

This paper describes linear cofactor relationships (LCRs), which are defined as the exclusive sums of cofactors with respect to a pair of variables in Boolean functions. These relationships subsume classical symmetries and single-variable symmetries. The paper proposes an efficient algorithm to detect LCRs and discusses their potential applications in Boolean matching, minimization of decision diagrams, synthesis of regular layout-friendly logic circuits, and detection of support-reducing bound sets

Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (SS 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications.

A new approach to the interconnect-driven floorplanning problem integrates bus planning and is intended for bus-based designs where each bus consists of a large number of wires. The floorplanner optimizes the timing and ensures routability by generating the exact location and shape of interconnects above and between the circuit blocks. Experiments with Microelectronics Center of North Carolina benchmarks clearly show the advantage of integrated floorplanning over the classical floorplan-analysis-and-then-refloorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12%-13% smaller in area as compared to traditional floorplanning algorithms.

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

A new kind of a decision diagrams are presented: its nodes correspond to all types of nonsingular expansions for groups of input variables, in particular pairs. The diagrams are called the Linearly Independent (LI) Decision Diagrams (LI DDs). There are 840 nonsigular expansions for a pair of variables, thus 840 different types of nodes in the tree. Therefore, the number of nodes in such (exact) diagrams is usually much smaller than the number of nodes in the well-known Kronecker diagrams (which have only single-variable Shannon, Positive Davio, and Negative Davio expansions in nodes). It is usually much smaller than 1/3 of the number of nodes in Kronecker diagrams. Similarly to Kronecker diagrams, the LI Diagrams are a starting point to a synthesis of multilevel AND/OR/EXOR circuits with regular structures. Other advantages of LI diagrams include: they generalize the well-known Pseudo-Kronecker Functional Decision Diagrams, and can be used to optimize the new type of PLAs called LI PLAs. Importantly, while the known decision diagrams used AND/EXOR or AND/OR bases, the new diagrams are AND/OR/EXOR-based. Thus, because of a larger design space, multi-level structures of higher regularity can be created with them. This paper presents both new concepts and new efficient synthesis algorithms.

This paper introduces a new design approach that combines stages of logic and physical design. The logic function is synthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitra cascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subset of inputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its result back to them. This two-dimensional geometrical model is well suited for both fine-grain FPGA realization and sea-of-gates custom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, and column folding, are discussed in more details to illustrate our general methodology.

In this paper the fitting problem for a new Application Specific State Machine Device, CY7C361, from Cypress Semiconductor is formulated and the solution is proposed. This fitting problem consists of mapping a netlist obtained from high-level synthesis into the chip’s physical resources. In general, a mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints and node multiplication (placing some nodes of the netlist graph in more than one node of the physical graph). Such formulation is quite general for a class of Complex Programmable Logic Device (CPLD) fitting problems, and has not been found in the literature. We implemented an exact, constraint-based, tree searching algorithm with several kinds of backtracking.

Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous incomplete circuit-based methods and complete BDD-based methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed.

Presented are new algorithms for synthesizing Boolean functions as regular logic structures. These regular structures can be mapped directly (without place&route) to a standard-cell library designed for regularity or to locally-connected programmable devices. The advantage of regular structures is that for a planar embedding the number of nodes in the expansion level grows at most linearly with the number of expansion variables. Regularity offers a predictable solution to hard problems arising in layout, at no extra cost or at the cost of increasing the number of gates, but without necessarily increasing circuit area. Increasing the number of logic levels does not translate into an increase in overall circuit delay, because regular, neighbor-to-neighbor connections reduce the wire delay, the dominant factor in deep sub-micron technology. This paper proposes new techniques which lead to less variable repetition and significantly improve the performance of synthesis algorithms. Experimental results much better than previously published data are very encouraging.

Detecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting support-reducing bound sets using two-cofactor symmetries. Experiments on the MCNC and ITC benchmarks show an average 40/spl times/ speedup over the published exhaustive method for bound set construction.

This special issue of the Springer Analog Integrated Circuits and Signal Processing (ALOG) presents the selection of best papers from the Third IEEE Latin American Symposium on Circuits and Systems (LASCAS 2012). The symposium, a forum for discussion of the latest technical novelties on circuits and systems topics, was held in Playa del Carmen, Mexico, from February 29 to March 2, 2012. 112 papers from 20 countries and 3 continents were submitted to the conference. 69 papers were accepted based on the reviews from international experts. These contributions made up a high-quality technical program covering a wide variety of subjects in the areas of analog and digital circuits and systems, computer aided design, modeling and simulation, signal processing, sensor systems, high-frequency systems, voltage references, processor architectures and control theory. From the papers presented at the conference, 12 papers were pre-selected for journal publication based on the evaluations of the Program Committee members and the corresponding session chairs. After a thorough revision of the extended papers, 7 papers were finally accepted for publication in this special issue. These contributions are: (1) an ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology; (2) a rail-to-rail differential quasi-digital converter for low-power applications; (3) analog sigma-delta modulation with op-amp gain compensation for nanometer technologies; (4) design of an integrated single-input dualoutput 3-switch buck converter based on sliding mode control; (5) offset and gain calibration circuit for MIMISFET devices; (6) parallel algorithm for evolvable-based boolean synthesis on GPUs; (7) neural inverse optimal control applied to type 1 diabetes mellitus patients. We thank the researchers from around the world who have chosen LASCAS 2012 for presenting their recent developments. We are deeply thankful to the reviewers for their contribution to the creation of the LASCAS 2012 technical program and for their involvement in the revision of the selected papers for this special issue. Finally, we thank the session chairs who not only contributed to the successful development of the symposium, but also helped in the selection of the best papers for journal publication.

A new class of non-totally symmetric functions which can be represented as simple regular symmetric arrays without redundancy is identified. Regular circuits are becoming crucially important for deep submicron technologies, which needs new layout approaches to fully utilized their potential. The new class of functions contains the classes of totally symmetric and totally symmetric with mixed polarities functions. Two circuit implementations are proposed, one especially aimed on low-power applications. Generating such functions with a simple method is also described.

The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing. The approach considers all nets simultaneously and the absence of a satisfying assignment implies that the layout is unroutable. We use two of the fastest SAT solvers: Chaff and DLM to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

This paper describes two families of canonical Reed-Muller forms, called inclusive forms (IFs) and their generalization, the generalized inclusive forms (GIFs), which include minimum ESOPs for any Boolean function. We outline the hierarchy of known canonical forms, in particular, pseudo-generalized Kronecker forms (PGKs), which led us to the discovery of the new families. Next, we introduce special binary trees, called the S/D trees, which underlie IFs and permit their enumeration. We show how to generate IFs and GIFs and prove that GIFs include minimum ESOPs. Finally, we present the results of computer experiments, which show that GIFs reduce the search space for minimum ESOP by several orders of magnitude, and this reduction grows exponentially with the number of variables.

A new, approximate method is presented to calculate a digital core supply current spectrum. The method is based on characterisation of supply current pulses in terms of the rise and fall times and pulse width. The upper limits (an envelope) for the supply current spectrum are derived using logic signal transition densities at digital core internal nodes. Contrary to the known methods, the proposed one uses limited data and generates much needed supply current information strongly desired by a system designer at a very early system planning. By using the probabilistic and statistical techniques the method is only weakly dependent on input sequence pattern and gives reliable final results.

A simple and fast algorithm for solving the two-terminal board level routing problem in FPGA-based logic emulation systems is presented. The method is based on the net scan selection process. Experimental results are the first implemented results for an algorithm presented previously. The comparison results show that the current approach achieves better effectiveness and uses less CPU time.

The BILOW simulation program for investigating bipolar transistor behavior in the temperature range 77-300 K is discussed. Differences between the numerical approaches required for simulation of low-temperature behavior compared to room-temperature simulation are presented. Efficient numerical models for the physical parameters in the carrier transport equations and Poisson's equation for the temperature range of 77-300 K, including a new highly accurate numerical model for the temperature and doping concentration dependence of carrier mobility, are discussed. A temperature- and doping-concentration-dependent model for apparent bandgap narrowing is also discussed. The internal characteristics of a typical bipolar transistor are simulated over the 300-77 K range. The behavior of current gain beta and the unity gain frequency f/sub T/ versus collector current density for different temperatures are calculated and discussed. >

Modifications to the MOSCAP computer program extend the temperature range down to 7 K, and gate voltage is introduced as an input parameter instead of surface potential. The modifications do not affect computational efficiency or accuracy.