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Board-level multiterminal net assignment for the partial cross-bar architecture
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:511-514
- Publication Year :
- 2003
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2003.
-
Abstract
- This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.
- Subjects :
- Very-large-scale integration
Computer science
Computability
Satisfiability
Boolean algebra
Computer Science::Hardware Architecture
symbols.namesake
Logic synthesis
Hardware and Architecture
Gate array
Maximum satisfiability problem
Hardware_INTEGRATEDCIRCUITS
symbols
Electrical and Electronic Engineering
Routing (electronic design automation)
Field-programmable gate array
Boolean satisfiability problem
Algorithm
Software
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 11
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........3ee878b58a1f3f20c9bc266317cde293