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To improve the power handling capability at ground stations of a 5.8-GHz solar space power satellite using microwave power transmission, a power charge-pump meta-semiconductor field-effect transistor (MESFET)-based rectifier is presented in this article. Unlike conventional microwave Schottky diodes, diode-connected MESFETs, whose nonlinear characteristics help them to have a unique current–voltage (I-V) curve that overcomes the limitations of a Schottky diode. Thus, the maximum input power of the proposed rectifier is extended up to 251.2 mW by replacing a Schottky diode with a diode-connected MESFET. Additionally, a class F harmonic processing network is introduced to control the voltage and current waveform at the load of the rectifier. Consequently, the RF-dc conversion efficiency is increased since the power dissipation is limited at the junction resistance of both the drain and the source of the MESFET. Owing to the abnormal characteristics of the diode-connected MESFET, the measured conversion efficiency of our rectifier is approximately 73.2% at 126 mW, and the input power range for rectifier efficiency higher than 50% is between 16 and 224 mW. The proposed rectifier for the space solar power satellite application is demonstrated and verified using a microwave wireless power transmission system. [ABSTRACT FROM AUTHOR]

Schottky contacts have been used to fabricate normally- OFF lateral reverse-blocking MESFETs on p-type (boron-doped) O-terminated monocrystalline diamond. The devices utilized an ohmic source contact but both gate and drain contacts were Schottky in nature. Boron-doped p-channel diamond MESFETs reported to date display the less attractive normally- ON characteristics. Here, the normally- OFF transistor delivered a current level of ~1.5 $\mu $ Amm−1 at a negative ${V}_{\text {GS}}$ of 0.8 V and a transconductance (${g}_{m}$) of $16~\mu $ Smm−1, measured at room temperature (RT); at a temperature of 425 K, these values rose to $\sim 70~\mu $ Amm−1 for ${I}_{\text {DS}}$ and a ${g}_{m}$ value of $260~\mu $ Smm−1. In both cases, a negligible gate leakage current was measured with no breakdown apparent at the maximum field investigated here ($3.7\times 10^{{5}}$ V/m−1). The Schottky gate demonstrates a well-behaved control of the channel even at higher temperatures. The high-temperature operation, normally- OFF behavior, and diamond’s inherent radiation hardness make this transistor promising for harsh environment applications. [ABSTRACT FROM AUTHOR]

Unintentional as well as intentional electromagnetic interference can cause interference and performance degradation of microwave circuits or systems. In this article, a modified multiport lumped-network finite-difference time-domain method (FDTD) method based on Y-matrix is proposed, where bilinear transform is used to incorporate the V–I relation of the lumped-network into FDTD iteration. It is further used for simulating transient responses of mesfet-based amplifiers, which are often used in many radar and communication systems. The excitation of such an RF amplifier is assumed to be an intentional electromagnetic interference (IEMI) signal but with different waveforms and magnitudes. Parametric studies are performed to show hybrid effects of waveforms and magnitudes of the IEMI signals on the transient coupled voltages at the output port of such mesfet-based amplifier, with useful information obtained for understanding the interaction process between the intentional electromagnetic interference signals and active components. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to predict DC characteristics of wide bandgap metal semiconductor field effect transistors (MESFETs). The model evaluates potential distribution inside the channel of the device by dividing the Schottky barrier depletion layer into four distinct regions and predicts I - V characteristics both at the room as well as at elevated temperatures. It also considers selfheating effects caused by the high-drain current and predicts negative output conductance, usually exhibited by wide bandgap MESFETs. The validity of the proposed technique is ensured by applying it on GaN and SiC MESFETs. It has been shown that the developed technique offers ~50% and ~37% improved accuracy in predicting the output characteristics of the device at T = 300 K and T = 500 K, respectively, relative to the best reported model. Thus, the proposed technique can be employed in the device modeling software involving high-power MESFETs.

This article reports the first comprehensive analysis of the reliability of hydrogen-terminated diamond metal semiconductor field-effect transistors (MESFETs) submitted to OFF-state stress. We demonstrate that stress induces an increase in ON-resistance and a shift in the threshold voltage, along with a decrease in the transconductance peak value. These effects are ascribed to the generation of defects at the diamond surface and/or in the upper semiconductor layers. The defects are generated both in the access regions and under the gate, and their activation energy is 0.30 eV. [ABSTRACT FROM AUTHOR]

In this article, we report the fabrication and characterization of boron-doped diamond (B-diamond) Schottky diodes and MESFETs. Effects of annealing at 573–973 K on the electrical properties of these devices are investigated. Current density maximum for the as-fabricated Schottky diode is 0.05 A/cm2 at a gate voltage of −10.0 V. Annealing at 673 and 973 K makes it increase first to 0.70 A/cm2 and decrease lately to 0.07 A/cm2, respectively. ON/OFF ratios for the as-fabricated B-diamond Schottky diode exceed 4.5 × 108 at the OFF-voltage (VOFF) of 0 V and 3.2 × 106 at VOFF = 42.0 V. For the annealed Schottky diode, the ON/OFF ratios are higher than 1.7 × 106 at VOFF < 6.0} V. Ideality factor and barrier height for Au/Pt bilayer gates on the B-diamond channel layer range from 1.05 to 1.78 and from 1.24 to 1.56 eV, respectively. All three B-diamond MESFETs with the gate lengths of 12.0, 7.0, and 4.3 μm, respectively, operate with p-type channel characteristics. The drain current maxima for the as-fabricated MESFETs are −0.11, −0.16, and −0.39 mA/mm. After annealing at 773 K, these values increase to −0.17, −0.24, and −0.55 mA/mm. Annealing at 773 K also increases the extrinsic transconductance maxima for the three MESFETs from 11.1, 11.0, and 10.4μS/mm to 18.6, 16.2, and 14.4 μS/mm, respectively. [ABSTRACT FROM AUTHOR]

This brief demonstrates the effectiveness of utilizing a 4-bit current steering digital to analog converter (DAC) as an adaptive power controller to adjust the dc quiescent current of a linear power amplifier as a function of the input signal power. A custom made metal-semiconductor field-effect transistor (MESFET), which is used as the amplifying transistor, and a current steering DAC have been integrated on the same substrate to minimize the power amplifier’s form factor and mismatches between the power tracker and the MESFET. This design has been implemented in a 45-nm CMOS SOI global foundries (GFs) process with a nominal supply voltage of 0.9 V and provides 31.8 dBm of output power, 45% peak efficiency and 24 dB maximum power gain. Measurement results at 70 MHz reveal about 10% efficiency improvement at 6-dB power back-off with continuous wave and 5% for standard 16-PSK EDGE modulated signals. The amplifier shows error vector magnitude of 5% and ACPR of −56.9 dBc at 400 kHz offset from the carrier frequency without digital pre-distortion, while transmitting 27 dBm of modulated output power. [ABSTRACT FROM AUTHOR]

A 2-D electrothermal model of delta-doped beta-gallium oxide (β-Ga2O3) metal–semiconductor field-effect transistor (MESFET) is developed by using TCAD Sentaurus to investigate its electrical and thermal characteristics. The temperature and electric field-dependent electron mobility model is incorporated to predict I–V characteristics of the FET, which are in good agreement with the measured I–V characteristics. We investigated the effect of bias voltages on an electric field, a current path, a volumetric heat generation profile, and a peak temperature at a given total heat dissipation. The peak temperature is observed to be significantly different at the same power dissipation but different bias conditions, e.g., the peak temperature is ~9 K higher when the drain-to-source voltage (Vds) = 25 V and the gate-to-source voltage (Vgs) = −6 V compared with Vds = 8.3 V and Vgs = 2 V at the total power dissipation of 1.16 W/mm. This difference is attributed to the change in the electron Joule heating profile with the applied bias voltage. The effects of the location of the delta-doping layer, the gate–drain spacing, and the source–drain spacing are investigated to guide a future device fabrication. The variation in these parameters mainly affects electrical characteristics such as ON-resistance, saturation current, threshold voltage, and so on. The thermal characteristics, such as peak temperature, temperature profile, and so on, are not significantly affected at a low-power dissipation. [ABSTRACT FROM AUTHOR]

Metal–semiconductor and junction n-channel field-effect transistors (MESFETs and JFETs) have been fabricated on glass substrates using room temperature deposited amorphous zinc–tin oxide (ZTO) channel layers. Characteristics of transistors and inverter circuits are compared. Best FET devices exhibit ON-to- OFF current ratios over eight orders of magnitude, subthreshold swings as low as 250 mV/dec and field-effect mobilities of 5 cm2/Vs. Furthermore, all devices show long-term stability over a period of more than 200 days. Inverters fabricated using either MESFETs or JFETs exhibit remarkable peak gain magnitude values of 350 and voltage uncertainty levels as low as 260 mV for an operating voltage of 5 V. A Schottky diode FET logic (SDFL) approach is applied to shift the switching voltage which is a requirement for cascading of inverters for realization of ring oscillators. [ABSTRACT FROM AUTHOR]

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a 45-nm silicon-on-insulator CMOS technology available from Global Foundries. MESFETs with gate lengths of 200 nm show good manufacturability with well-controlled run-to-run variations. The DC and RF performance of devices with different drain access lengths are compared to illustrate the design trades between high breakdown voltage and high frequency operation. Two applications of the MESFETs for RF integrated circuit design are presented. The first demonstrates integrated n-channel MOSFET–MESFET cascode amplifiers that combine the enhanced voltage operation of the MESFET with the high frequency capability of the scaled MOSFET. The resulting small-signal amplifiers demonstrate cut-off frequencies of 50 GHz when operated with supply voltages of 6 V, significantly higher than the nominal 1 V breakdown voltage of the CMOS transistors. The second application demonstrates a watt-level MESFET power amplifier integrated with a CMOS current steering digital-to-analog converter (DAC). The MESFET serves as the RF output device, while the 4-bit CMOS DAC enables average power tracking. Both examples demonstrate the design flexibility enabled by the CMOS-compatible MESFETs. [ABSTRACT FROM AUTHOR]

With the development of novel device applications, e.g., in the field of Internet of Things or point-of-care personalized diagnostic systems, came an increased demand for MESFETs for fast and low-power consumption integrated circuits and active-matrix displays. In this paper, we present fabrication and characterization of transparent Ru–Si–O/In–Ga–Zn–O MESFETs on flexible substrates. The use of transparent conducting oxide, namely, Ru–Si–O, as Schottky gate electrode, allows for processing the devices at room temperature, enabling the utilization of such low-temperature substrates as polyethylene terephthalate foil and paper. It was shown that tuning the device geometry allows realization of transistors providing on-current up to 2 mA, while the highest on-to-off current ratio equals 2\times 10^\mathrm 5 , with off-current below 1 nA, carrier mobility in the channel exceeds 9 cm ^\mathrm 2\cdot \textV^\mathrm -1\cdot \texts^\mathrm -1 , and subthreshold swing is below 250 mV $\cdot $ decade ^{\mathrm { {-1}}} . [ABSTRACT FROM PUBLISHER]

Silicon metal–semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, $\alpha $ , which agrees with three earlier data sets over nearly four orders of magnitude. [ABSTRACT FROM PUBLISHER]

We describe the development and optical characterization of a planar medium infrared (mid-IR) InSb photodetector on a GaAs substrate technology, capable of integrating MESFETs, to demonstrate a new active pixel device architecture. Our results pave the way for the development of integrated mid-IR focal plane array circuits on a single chip. Device structures with areas down to 0.0016 mm $^{{ {2}}}$ were investigated. By deploying a silicon nitride passivation layer, we were able to reduce leakage current in reverse bias by up to 27% to yield an improved rectifier. Extensive optical characterization was carried out in the near- and mid-IR wavelength range. Responsivities of up to 3.54 A/W and quantum efficiency values above unity were obtained in the near-IR range as a consequence of illumination above the bandgap causing impact ionization. In the mid-IR range, responsivities of up to 0.97 A/W were observed. The bandwidth of the devices proved compatible with video-rate standard sampling rates. [ABSTRACT FROM PUBLISHER]

Medium wavelength infrared (MWIR) detectors are of increasing importance in defense, security, commercial, and environmental applications. Enhanced integration will lead to greater resolution and lower cost focal plane arrays (FPAs). We present the monolithic fabrication of an active photopixel made in InSb on a GaAs substrate that is suitable for large-scale integration into an FPA. Pixel addressing is provided by the cointegration of a GaAs MESFET with an InSb photodiode (PD). Pixel fabrication was achieved by developing novel materials and process steps, including isolation etches, a gate recess etch, and low temperature processes, to make Ohmic contacts to both the GaAs and InSb devices. Detailed electrical and optical measurements in an FTIR demonstrated that the PD was sensitive to radiation in the range of 3– 5~\mu \textm at room temperature, and that the device could be isolated from its contacts using the integrated MESFET. This heterogeneous technology creates great potential to realize a new type of monolithic FPA of addressable pixels for imaging in the MWIR range. [ABSTRACT FROM AUTHOR]

This paper demonstrates the use of cost-effective solution-processed \alpha -Ga2O3 thin films (TFs) for electronic device applications. MESFETs based on AgOx Schottky diode (SD) gates were fabricated on highly crystalline Sn-doped \alpha -Ga2O3 TFs, grown by mist chemical vapor deposition at atmospheric pressure and a substrate temperature of only 400 °C. The rectification ratio and reverse breakdown voltage of typical SDs were 6 \times 10^6 and 19.6 V, respectively. The ON–OFF ratio of the corresponding transistors was 2 \times 10^7 . The MESFETs that could withstand drain voltages of up to 48 V were also realized. [ABSTRACT FROM AUTHOR]

This paper is an important step toward the development of complex integrated circuit (IC) control electronics that have to attend to high-temperature environment power applications. We present in premiere a prototype set of essential mixed-signal ICs on SiC capable of controlling power switches and a lateral power MESFET able to operate at high temperatures, all embedded on the same chip. Also, we report for the first time the functionality of standard Si-CMOS topologies on SiC for the master–slave data flip-flop (FF) and data-reset FF digital building blocks designed with MESFETs. Concretely, we present the complete development of SiC-MESFET IC circuitry, able to integrate gate drivers for SiC power devices. This development is based on the mature and stable Tungsten–Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo. [ABSTRACT FROM PUBLISHER]

In this paper, an analysis of gate–source and gate–drain scaling effects in MESFETs fabricated on hydrogen-terminated single-crystal diamond films is reported. The experimental results show that a decrease in gate–source spacing can improve the device performance by increasing the device output current density and its transconductance. On the contrary, the gate–drain distance produces less pronounced effects on device performance. Breakdown voltage, knee voltage, and threshold voltage variations due to changes in gate–source and drain–source distances have also been investigated. The obtained results can be used as a design guideline for the layout optimization of H-terminated diamond-based MESFETs. [ABSTRACT FROM AUTHOR]

In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too. [ABSTRACT FROM PUBLISHER]

A novel backgate modulation technique alleviating limitations associated with supply-regulated polar transmitters is proposed. The backgate of a partially depleted silicon-on-insulator metal–semiconductor field-effect transistor with a breakdown voltage of 15 V is used to modulate the gain and output power of an RF power amplifier (PA). The high-impedance backgate provides high-efficiency and wide-dynamic-range modulation of PA gain. Measured results at 1.8 GHz demonstrate 16% power-added efficiency improvement at 6-dB backed-off output power, compared with the same RF PA without backgate modulation. [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator metal–semiconductor field-effect transistor (SOI MESFET) with controlled electric field distribution is presented in this brief. An additional layer of oxide (LO) is located in the device channel region in order to supervise the electric field distribution. The simulation results show that the LO region has excellent effects on the breakdown voltage of the device, which increases by 50% compared with that of the conventional SOI MESFET structure. Also, the maximum output power density improves by 53%. In addition, the LO region causes the improvement of the device gains and frequency parameters. Consequently, the novel SOI MESFET structure has superior electrical characteristics compared with the similar device based on the conventional structure. [ABSTRACT FROM PUBLISHER]

In this paper, a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) with modified charge distribution is presented. Changing charge distribution leads to lower electric field crowding and increased breakdown voltage (VBR). For modifying charge distribution, a metal region (MR) is utilized in buried oxide of the SOI MESFET. In order to achieve the best results, the MR location and dimensions are optimized carefully. DC and radio frequency characteristics of the SOI MESFET with MR (MR-SOI MESFET) are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-SOI MESFET) characteristics. The simulated results show that the MR has excellent effect on the VBR of the device. The VBR of the MR-SOI MESFET structure improves by 116% compared with that of the C-SOI MESFET structure. Although drain current of the proposed structure reduces slightly, 126% improvement in maximum output power density of the device is achieved due to high enhancement of the VBR. Also, the MR leads to the enhancement of maximum oscillation frequency and maximum available gain of the MR-SOI MESFET structure. As a result, the MR-SOI MESFET structure has superior electrical performances in comparison with the similar device based on the conventional structure. [ABSTRACT FROM PUBLISHER]

Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (IDSAT ≥ ), high operating frequency (fmax > 35 ) or enhanced breakdown voltage (VBD > 25). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications. [ABSTRACT FROM AUTHOR]

In this paper, a consistent gate charge model for GaAs MESFETs based upon charge conservation is proposed for monolithic microwave integrated circuit power amplifier designs. This new model is capable of accurately modeling the transistor under various biasing conditions. The conventional approaches for charge modeling of GaAs MESFETs usually adopt analytical equations to fit nonlinear gate capacitors separately, which might be difficult to implement in circuit simulators whose capacitance is always the derivative of an internal state variable (charge). Moreover, compared with the conventional diode and Statz model, the performance prediction in the linear region, saturation knee region, and subthreshold region is greatly improved. Measured and modeled results of a 2\,\times\,150 \mu\ m GaAs MESFET are compared and good agreement has been obtained. Comparisons between the proposed model, diode junction model, and Statz model are also presented in this paper. In addition, a class-AB Ku-band power amplifier using a 0.18-\mu\ m GaAs MESFET process was designed with the new model for verification of the new model accuracy. [ABSTRACT FROM PUBLISHER]

Metal–semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal–oxide–semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = \150\ \nm have a current drive that exceeds 200 mA/mm with a peak fT > \35\ \GHz. This is considerably higher than the Lg = \400\ \nm MESFET with a current drive of \sim70 mA/mm and a peak fT = \10.6\ \GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <\break \400\ \nm, resulting in an optimum MESFET gate length for this technology in the range of 200–300 nm. [ABSTRACT FROM PUBLISHER]

GaAs nanowire (NW)-based metal–semiconductor field-effect transistors (MESFETs) were constructed on flexible plastic substrates by a conventional top–down approach. The top–down approach utilized in this paper combines photolithography of high-quality GaAs bulk wafers with anisotropic chemical etching processes for preparation of GaAs NWs and photolithographic processes for formation of metal electrodes. For a representative GaAs NW-based MESFET, peak transconductance, the Ion/Ioff ratio, and the subthreshold slope are estimated to be approximately 19.7 \mu\S, \sim\!\!\10^7, and \sim100 mV/dec, respectively. The electrical characteristics of the GaAs NW-based MESFETs were maintained during 3000 times of bending cycles under maximal tensile strains of 0.77% and 1.02%. These results demonstrate the possibility of using these devices in high-speed and high-performance flexible electronics. [ABSTRACT FROM AUTHOR]

In this paper, we carry out a 2-D transient analysis of field-plate GaAs metal–semiconductor field-effect transistors (FETs) by taking surface states into account. Quasi-pulsed current–voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates the trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and the \SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and the \SiO2 layer thickness. [ABSTRACT FROM PUBLISHER]

The influence of field plates and surface traps on silicon carbide MESFETs for microwave operation was investigated. By increasing the length of gate-connected field plates from 50 to 800 nm, it was possible to increase the gate-drain breakdown voltage of the devices from 125 to 170 V. At the same time, the current slump effect of traps in the passivation oxide was reduced. By using a combination of field plates and a passivation oxide with low interface trap density, it was possible to reach an output power density of 8 W/mm at 3 GHz. [ABSTRACT FROM AUTHOR]

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 μm. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 μm and an access length of 0.6 μm, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V. [ABSTRACT FROM AUTHOR]

Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data. [ABSTRACT FROM AUTHOR]

A comprehensive analysis of a multistage Doherty amplifier, which can be used to achieve higher efficiency at a lower output power level compared to the classical Doherty amplifier, is presented. Generalized design equations that explain the operation of a three-stage Doherty amplifier, which can be easily extended to an N-stage Doherty amplifier, are derived. In addition, the optimum device periphery, which minimizes AM-AM distortion for perfect Doherty amplifier operation, is analyzed. For the first time, a multistage Doherty power amplifier that meets wide-band code-division multiple-access (WCDMA) requirements is demonstrated. The designed power amplifier exhibits a power-added efficiency (PAE) of 42% at 6-dB output power backoff and 27% at 12-dR output power backoff. These PAEs are more than 2× and 7× better, respectively, than that of a single-stage linear power amplifier at the same output power backoff levels. The power amplifier is capable of delivering up to 33 dBm of output power, and has a maximum adjacent channel power leakage ratio of -35 and -47 dBc at 5- and 10-MHz offset, respectively. To the best of the authors' knowledge, these represent the best reported results of a Doherty amplifier for WCDMA application in the 1.95-GHz band to date. [ABSTRACT FROM AUTHOR]

In this paper, a novel approach to the measurement of mobility of GaAs HEMT devices is presented. The new approach employs high-order derivatives as a means of determining the parameters of the proposed new mobility equation. The new approach is compared to established mobility measurement methods, and shown to offer better accuracy. The results presented also consider the behavior of mobility in the linear and saturation bias regions. The mobility value extracted by this new method has permitted improvements to the MESFET/HEMT model when simulating the behavior of the device in the linear region. This is critical in many applications, such as in low current linear-mixing applications. [ABSTRACT FROM AUTHOR]

We present a theoretical study of metal-semiconductor field-effect transistor (MESFET) devices for three different materials: zincblende-phase gallium nitride (ZB-GaN), cubic-phase silicon carbide (3C--SiC) and gallium arsenide (GaAs). The dc breakdown voltage of comparable MESFETs made with the two wide bandgap materials, ZB--GaN and 3C--SiC are compared to that made with the well studied material, GaAs. In this way, the GaAs calculations serve as a control, enabling an accurate comparison of the device behaviors. The simulations are performed with a new, generalized, self-consistent, full-band Monte Carlo simulator. The new simulator includes fully numerical scattering rates and a fully numerical, overlap-based final-state selection process. A 0.1μm gate-length MESFET is used for all of the simulations, and rectangular wells of lightly doped material are used to model interface states. The calculated dc breakdown voltages of the ZB--GaN, 3C-SiC, and GaAs MESFETs are 18, 16, and 5 V respectively. The previously estimated factor-of-four difference between the breakdown voltage of ZB--GaN and GaAs devices is verified. [ABSTRACT FROM AUTHOR]

This paper describes a miniaturized monolithic-microwave integrated-circuit (MMIC) analog phase shifter using two quarter-wave-length transmission lines. A conventional analog phase shifter employs an analog phase-shifter topology using a 3-dB 90° branch-line hybrid requiring four quarter-wave-length transmission lines. Thus, in the first stage of our study, we present a new analog phase-shifter topology using only two quarter-wave-length transmission lines. The phase shifter here has only one-half as many transmission tines as a conventional analog phase shifter using a 3-dB 90° branch-line hybrid, and the circuit can be miniaturized to less than one-fourth as compared to the conventional analog phase shifter. Furthermore, we show that the operating frequency range of the phase shifter is very wide and can obtain large phase variation with small capacitance variation. Next, an experimental Ku-band MMIC analog phase shifter is presented. A phase shift of more than 180° and an insertion loss of 3.6±1.1 dB are obtained at the frequency range from 12 to 14 GHz. The chip size of the experimental MMIC phase shifter is less than 3.0 mm2 [ABSTRACT FROM PUBLISHER]

A phenomenologically based transient SPICE model was developed for GaAs MESFETs. The model accounts for both trapping and detrapping effects; hence, it can simultaneously simulate low-frequency dispersion and gate-lag characteristics. This is different from conventional models, which can simulate either effect, but not both. The present model has been used to describe both surface- and substrate-related trapping phenomena in epitaxial or ion-implanted MESFETs. The model was experimentally verified in terms of pulsed I-V characteristics and pulsed AC response [ABSTRACT FROM PUBLISHER]

In the paper a balanced high power amplifier with class A silicon bipolar transistors for L-band T/R module is described. The amplifier was designed for maximum power and minimum transmitance distortions. The obtained parameters of the amplifier are as follow: output power at 1 dB compression P1 dB > 49 dBm, linear gain |S21| > 10 dB, and transmitance deviations during the RF pulse: phase arg(S21)

This paper reports a study on the fabrication technology of high performance functional devices, where high temperature superconductor and compound semiconductor devices are monolithically integrated on the same substrate. We investigated optimal conditions for epitaxial liftoff process and succeeded in fabricating HTS device and GaAs MESFET on SrTiO/sub 3/ substrate without degrading characteristics of superconductor and semiconductor devices. We also carried out basic integrated circuit fabrication processes such as patterning and etching for quasi-monolithic structure. The results confirmed that fabricating high performance functional devices is feasible. [ABSTRACT FROM PUBLISHER]

To meet the specifications of future radar and communication systems we developed a low phase noise microwave oscillator. This feedback oscillator consists of a commercial MESFET-amplifier at room temperature and a LaAlO/sub 3/ dielectric resonator with high temperature superconducting (HTS) shielding at 63 K. The resonator operating at a resonance frequency of 5.6 GHz showed unloaded quality factors in the 10/sup 5/ to 10/sup 6/ range. By means of a strong resonator coupling (|S/sub 21/|=6 dB) and an amplifier gain of 20 dB we obtained an output power of +15 dBm. The phase noise L(f/sub m/) of the oscillator was below the detection limit for offset frequencies beyond 10 kHz. For offset frequencies below 5 kHz measurements revealed perfect L(f/sub m/)/spl prop/f/sub m//sup .3/-behaviour according to the Leeson model. The phase noise was -110 dBc/Hz at 1 kHz offset and -130 dBc/Hz at 10 kHz. This phase noise performance is superior to state of the art SAW- or quartz oscillators for f/sub m/>10 kHz. To further reduce the phase noise performance close to the carrier we investigated the implementation of a phase locked loop (PLL). The long term temperature stability of the oscillator frequency can be enhanced by introducing a central cylinder made from rutile (TiO/sub 2/). We present numerical and experimental results on this compensation. [ABSTRACT FROM PUBLISHER]