Search

Within this paper, we present a novel, straightforward progressive encoding scheme for general triangle soups, which is particularly well-suited for mobile and Web-based environments due to its minimal requirements on the client's hardware and software. Our rapid encoding method uses a hierarchy of quantization to effectively reorder the original primitive data into several nested levels of detail. The resulting stateless buffer can progressively be transferred as-is to the GPU, where clustering is efficiently performed in parallel during rendering. We combine our approach with a crack-free mesh partitioning scheme to obtain a straightforward method for fast streaming and basic view-dependent LOD control.

In order to render 3-D graphics efficiently, rasterization techniques have been developed. Traditional clipping techniques using six-planes of view volume are complicated and not cost-effective. This paper develops a novel cost-effective strategy for primitives with regard to clipping in rasterization. Throughout the process, no expensive clipping action is required and no extra clipping-derived polygons are produced. It also presents the architecture of a 200-MHz multicore, multi-thread 3-D graphics SoC in 65nm 1P9M process with a core size of 4.97mm2 and 153.3mW for power consumption. The proposed clip-less architecture in rasterization processes the valid screen space region of each primitive in eight cycles, with a gate-count of only 20k. In addition, the throughput can achieve up to 25 M Triangles/Sec.

Embedded systems in several applicationsrequire a graphics system to displaysome application-specific information. Yet, commercial graphic cards for the embedded systems either incur high costs, or they are inconvenient to use. Furthermore, they tend to quickly become obsolete due to the advances in display technology. On the other hand, FPGAs provide reconfigurable hardware resources that can be used to implement graphics system in which they can be reconfigured to meet the ev er-evolving requirements of graphics systems. Motivated from this fact, this study considers the design and implementation of a 2D graphics system on FPGA. The graphics system proposed is composed of a CPU IP core, peripheral IP cores (Bresenham, BitBLT, D DR Memory Controller, and VGA) and PLB bus to which CPU and all peripheral IP cores are attached. Furthermore, some graphics drivers and APIs are developed to complete the whole graphics creation process.

A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation.

Currently, memory bandwidth has become the main bottleneck in graphics system. Reducing the memory access can reduce the power consumption and boost overall system performance. Low power technique is more important for graphics applications on hand-held or mobile device. In this paper, we propose a novel visibility driven rasterizer to reduce the memory access and operations on invisible pixels. It integrates with two-level hierarchical Z-buffer to do visibility driven rasterization. The rasterization scheme is tile-order scan-line based, and the rasterizer can smartly change the tile-size depending on the triangle size. This technique can balance the rasterization loading under different triangles. Moreover, we propose a fast visibility test algorithm to quickly reject a group of pixels within the tile. Simulation results show that the overall bandwidth reduction can be up to 60% under our test images.

Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.

Increasingly, 3D graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsu's chip set solves that problem using two processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines.

The Siggraph/Eurographics Graphics Hardware 2003 workshop, held in San Diego, will likely be remembered as a turning point in modern computing. In one of those rare moments when a new paradigm visibly begins changing general-purpose computing's course, what has traditionally been a graphics-centric workshop shifted its attention to the nongraphics applications of the graphics processing unit. GPUs, made by Nvidia (www.nvidia.com) and ATI (www.ati.com), function as components in graphics subsystems that power everything from Microsoft's Xbox to high-end visualization systems from Hewlett-Packard and SGI. The GPUs act as coprocessors to CPUs such as Intel's Pentium, using a fast bus such as Intel's Advanced Graphics Port. AGP8x has a peak bandwidth of 2.1 gigabytes per second - speed it needs to avoid inflicting bus starvation on data-hungry GPU coprocessors.

Recent applications of computer software to water resources and environmental master-planning studies include use of graphical displays in order to disseminate information. In this paper, a simple-to-use graphics display program is presented which enables a user to display graphical slides, stored on disk, to the CRT. Such a program enables a user to link graphics slides to next data by use of a read-only text display routine. Application of the provided program in a Graphics Data Base Management System is considered as a case study. Computer code is provided for the graphics slide display.

This paper presents a novel method for using programmable graphics hardware to generate fringe patterns for SLM-based holographic displays. The algorithm is designed to take the programming constraints imposed by the graphics hardware pipeline model into consideration, and scales linearly with the number of object points. In contrast to previous methods we do not have to use the Fresnel approximation. The technique can also be used on several graphics processors in parallel for further optimization. We achieve real-time frame rates for objects consisting of a few hundred points at a resolution of 960 × 600 pixels and over 10 frames per second for 1000 points.

Graphics and vision are approximate inverses of each other: ordinarily graphics processing units (GPUs) are used to convert ldquonumbers into picturesrdquo (i.e. computer graphics). In this paper, we discuss the use of GPUs in approximately the reverse way: to assist in ldquoconverting pictures into numbersrdquo (i.e. computer vision). For graphical operations, GPUs currently provide many hundreds of gigaflops of processing power. This paper discusses how this processing power is being harnessed for image processing and computer vision, thereby providing dramatic speedups on commodity, readily available graphics hardware. A brief review of algorithms mapped to the GPU by using the graphics API for vision is presented. The NVIDIA CUDA programming model is then introduced as a way of expressing program parallelism without the need for graphics expertise.

In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magnitude greater than the growth in the power of computer processor units. Thus these graphics cards are now beginning to be used by the scientific community aslow cost, high performance computing platforms. Traditional genetic programming is a highly computer intensive algorithm but due to its parallel nature it can be distributed over multiple processors to increase the speed of the algorithm considerably. This is not applicable for single processor architectures but graphics cards provide a mechanism for developing a data parallel implementation of genetic programming. In this paper we will describe the technique of general purpose computing using graphics cards and how to extend this technique to genetic programming. We will demonstrate the improvement in the performance of genetic programming on single processor architectures which can be achieved by harnessing the computing power of these next generation graphics cards.

Commodity graphics hardware has become increasingly programmable over the last few years but has been limited to fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. In this paper, we explore one solution to this problem using compile-time resource allocation. For our experiments, we implement a graphics pipeline on Raw, a tile-based multicore processor. We express both the full graphics pipeline and the shaders using StreamIt, a high-level language based on the stream programming model. The programmer specifies the number of tiles per pipeline stage, and the StreamIt compiler maps the computation to the Raw architecture.We evaluate our reconfigurable architecture using a mix of common rendering tasks with different workloads and improve throughput by 55-157% over a static allocation. Although our early prototype cannot compete in performance against commercial state-of-the-art graphics processors, we believe that this paper describes an important first step in addressing the load-balancing challenge.

Author(s): Kniss, Joe M.; Lefohn, Aaron; Strzodka, Robert; Sengupta, Shubhabrata; Owens, John D. | Abstract: We implement an interactive 3D painting application that stores paint in an octree-like GPU-based adaptive data structure. Interactive painting of complex or unparameterized surfaces is an important problem in the digital film community. Many models used in production environments are either difficult to parameterize or are unparameterized implicit surfaces. We address this problem with a system that allows interactive 3D painting of complex, unparameterized models. The included movie demonstrates interactive painting of a 817k polygon model with effective paint resolutions varying between 64^3 to 2048^3. Our implementation differs from previous work in two important ways: first, it uses an adaptive data structure implemented entirely on the GPU, and second, it enables interactive performance with high quality by supporting quadlinear (mipmapped) filtering and fast, constant-time data accesses.

Texture mapping has become so ubiquitous in real-time graphics hardware that many systems are able to perform filtered texturing without any penalty in fill rate. The computation rates available in hardware have been outpacing the memory access rates, and texture systems are becoming constrained by memory bandwidth and latency. Caching in conjunction with prefetching can be used to alleviate this problem. In this paper, WC introduce a prefetching texture cache architecture designed to take advantage of the access characteristics of texture mapping. The structures needed are relatively simple and arc amenable to high clock rates. To quantify the robustness of our architecture, we identify a set of six scenes whose texture locality varies over nearly two orders of magnitude and a set 01 four memory systems with varying bandwidths and latencies. Through the use of a cycle-accurate simulation, we demonstrate that even in the presence of a high-latency memory system, our architecture can attain at least 97% of the performance of a zerolatency memory system. CR

FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. The first is to convert the read-modify-write Z-buffer compare and RGBa blend into a single write only operation. The second is to support two levels of rectangularly shaped pixel caches internal to the memory chip. The result is a 10 megabit part that, for 3D graphics, performs read-modify-write cycles ten times faster than conventional 60 ns VRAMs. A four-way interleaved 100MHz FBRAM frame buffer can Z-buffer up to 400 million pixels per second. Working FBRAM prototypes have been fabricated.

A program was written in assembly language for fast graphics screen dump of neurophysiological data during and after experiments. This program takes approximately 3 s to plot a 1024 x 768 graphics image. A resident program has also been produced, which allows a screen graphics image to be printed by using a keyboard command. A Pascal-compatible object file is available to interface the program with Turbo-Pascal programs.

Our work over the past several years has explored multicomputer architectures for three dimensional graphics that offer the promise of scalability, very high performance, and greater flexibility and range of application than today's systems. While current high performance commercial graphics systems employ various forms of parallelism to support interaction with 3D objects and scenes, all operate on a single stream of graphics primitives. Much of our effort has been devoted to finding ways to operate in parallel both on lists of graphics primitives as well as on the pixels within primitives, and to incorporate parallel execution of user application code to generate and modify the graphics primitives to be displayed.

The authors discuss the TMS34010, a high-performance 32-bit microprocessor with special instructions and hardware for handling the bit-field data and address manipulations often associated with computer graphics. They give a history of embedded microprocessors and examine the wide range of processors and applications covered by that term. They provide an overview of the internal architecture of the TMS34010 and discuss the choice of feature set in its design. Although it is aimed at graphics systems, the processor's large address reach, bit-field processing, and DRAM (dynamic random-access memory) interface make it suitable for many other embedded processing applications. >

This paper describes a system in operation at the University of British Columbia for structural analysis using interactive computer graphics. The three major components of such a system are a central processing unit, some graphics hardware, and software. The central processing unit should allow fast interactive use of the graphics hardware to eliminate long time delays for the designer. The minimum graphics hardware is a storage tube terminal for the display of vectors and diagrams. The addition of a hard copy unit will relieve the designer from the inevitable pressure of an interactive system and provide time to study the results of an analysis. Finally, a tablet provides for fast input and alteration of data, both geometric and numerical. These three pieces of graphics equipment, terminal, tablet, and copy unit, form an efficient input-output system.Software programs are of two varieties. The first will produce a common data bank via the tablet or generators. The second will draw from that bank for a variety of analyses such as linear, elastoplastic, second order, or dynamic. In all cases the analysis programs plot on the screen scale diagrams of axial, shear, moment, and deflection for instant hard copy. This integrated system of hardware and software provides an efficient analysis tool for both students and practising engineers.

The development of minisupercomputers is discussed. These desk-side units combine interactive, high-resolution graphics and vector processing. Available and soon-to-be-available minisupers are described. Vector processing, used by all these machines, is examined, as is virtual memory, another key feature. The advanced compiler and graphics facilities of the minisupers are described. >

A general-purpose graphics package is described that allows the user to generate figures with a supraset of the basic CalComp plotting subroutines. The software runs under RT-11 on an LSI-11 with 28K words of memory. The graphics subroutine library is approximately 200 blocks long. The plotting tasks are passed over an RS 232 line to a simple extension of an inexpensive and commercially available graphics controller. The controller implements these tasks as plotting instructions to a color television, a vector display, and a digital plotter. The graphics subroutines are written in FORTRAN and are invoked by the user as subroutine calls from a FORTRAN program. The graphics controller is a modified Motorola “Micro Chroma 68 Kit.” The board is based on the 6808 microprocessor and 6847 video controller. It provides eight graphic modes from 64 by 32 eight-color graphics to 128 by 192 four-color graphics to 256 by 192 two-color graphics. The present software and hardware implements the graphics subroutines as 256 by 192 two-color graphics, as 512 by 512 vector graphics, and as stepping instructions for a digital plotter.

The availability of inexpensive minicomputers and low cost digital/analog conversion equipment enables one to use interactive graphics in situations where such techniques were previously infeasible. The University of Tulsa is presently developing an interactive graphics package entitled BANDMARCH to assist the choreography of marching band drills. The graphics hardward consist of a 32K Interdata Model 70 minicomputer, a 5MB Diablo Disc system, a Tektronix 603 monitor with 256 × 256 point display provided by a pair of Detel 8 bit D/A converters. The program enables a band director who is most likely not computer oriented to prepare a routine in an existing language (About Face, Left Flank) and view the result of his ‘design’ in real time. The obvious interactive features of editing, cataloguing and accessing standard functions must be provided in a way that can be easily understood. T.U.'s BANDMARCH (not an acromym) provides such features. Common data structures in a relatively novel environment are a demonstration of the soundness of these techniques to an interactive graphics situation.

The use of the 16-bit ADSP-2100 digital signal microprocessor as a fixed-point, low-end graphics engine for applications such as video games and small computer graphics packages is examined. It serves as the basis for a complete, hardware-oriented approach to performing graphics operations on a 3-D database. Normalization and formatting are performed to avoid overflow and preserve data formats through the transformation operation. Data structures that facilitate object rendering through the Bresenham line-segment drawing algorithm are used. A 3*3 rotation matrix is derived for this application, and the means for implementing translation, scaling, perspective, and zooming are described. >

Until recently, most computer graphics systems have been oriented toward the display of line drawings, continually refreshing the screen from a display list of vectors. Developments such as plasma panel displays and rapidly declining memory prices have now made feasible raster graphics systems, which instead associate some memory with each point on the screen, and display points according to the contents of the memory. This paper discusses the advantages and limitations of such systems. Raster systems permit operations which are not feasible on vector displays, such as reading directly from the screen as well as writing it, and manipulating two dimensional areas as well as vectors. Conceptual differences between programming for raster and vector systems are illustrated with a description of the author's TV Turtle , a graphics system for raster scan video display terminals. This system is imbedded in Logo, a Lisp-like interactive programming language designed for use by kids, and is based on Logo's turtle geometry approach to graphics. Logo provides powerful ideas for using graphics which are easy for kids to learn, yet generalize naturally when advanced capabilities such as primitives for animation and color are added to the system.

GSP, a graphics software package that supports a high resolution interactive raster graphics terminal, is described. The software is primarily designed to provide portable elements for supporting interactive graphics terminals in various hardware configurations. The graphics library, which contains 2-D graphics functions based on Graphical Kernel System as well as some 3-D graphics functions, has been implemented. The Graphics Software Package includes Graphics System Support software as the main component in order to realize the following: one level of segmentations, image transformation, viewing in 2-D and 3-D, planar geometric projections and clipping. It also uses Basic System Support to provide facilities for the efficient control of the graphical peripherals, such as joysticks, tablets and light pens. Most of the graphics software has been written in C language and is designed to be almost entirely machine independent.

The Video Display Processor (VDP)*, a single chip video display system, is presented in this paper. The VDP provides high resolution color pattern graphics in combination with object oriented graphics, for display on an ordinary television receiver or simple monitor.

The IBM 3277 Graphics Attachment is an interactive computer graphics workstation using a dual-screen concept. A storage display monitor is attached to an IBM 3277 Display Station, the combination providing low-cost, moderate-performance interactive graphics. This paper describes the architecture of the Graphics Attachment, both functional structure and rationale. Nonarchitectural characteristics are also considered.

This paper discusses a system called DISPLAYTRAN that interpretively executes FORTRAN statements entered at a display console, allowing graphics users to perform unanticipated computations and to more easily debug graphics application programs. The relationships among the operating system, the display terminal, and the computing system are discussed, and the major components of this system are described. A command language, the FORTRAN IV subset, and the graphics language provided for users are presented. Internal operation of the graphic facility is outlined.

Colour graphics subsystems can be used in a variety of applications such as high-end business graphics, low-end scientific computations, and for realtime display of process control diagrams. The design of such a subsystem is shown. This subsystem can be added to any Multibus-compatible microcomputer system. The use of an NEC 7220 graphics display controller chip has simplified the design to a considerable extent. CGRAM (CORE graphics on Multibus), a comprehensive subset of the CORE graphics standard package, is supported on the subsystem.

The normal method of drawing in colour graphics systems with a number of memory planes is either to write separately on each plane or to write simultaneously on all planes. The first of these has the advantage of being flexible with respect to the number of memory planes, but it is very slow compared to the second. Writing simultaneously on all planes requires changes in basic drawing hardware for every addition to the number of memory planes. This paper attempts to introduce flexibility into the second approach: with the same basic drawing hardware and some external hardware, drawing can be performed on all planes simultaneously. The extra hardware does not demand any changes in the circuit timing parameters. A large portion of the extra hardware can be put on a programmable array logic (PAL) chip. The paper also presents an overview of an implementation of this approach, using the 82720 graphics display controller.

Los Alamos Scientific Laboratory (LASL) has implemented a graphics system designed to support one user interface for all graphics devices in all operating environments at LASL. The Common Graphics System (CGS) will support Level One of the graphics standard proposed by the ACM/SIGGRAPH Graphic Standards Planning Committee. CGS is available in six operating environments of two different word lengths and supports four types of graphics devices. It can generate a pseudodevice file that may be postprocessed and edited for a particular graphics device, or it can generate device-specific graphics output directly. Program overlaying and dynamic buffer sharing are also supported. CGS is structured to isolate operating system dependencies and graphics device dependencies. It is written in the RATFOR (RATional FORtran) language, which supports control flow statements and macro expansion. CGS is maintained as a single source program from which each version can be extracted automatically.

A low-cost Multibus-compatible graphics generator has been designed for a resolution of 512 × 512 pixels with a 3-bit colour code per pixel. The heart of the system is an 82720 graphics display controller (GDC). Usual designs of colour graphics generators use three different memory planes, each containing information corresponding to one of the three primary colours of the cathode ray tube (CRT). However, this approach requires a large PCB area and a large number of memories and transceivers. Further, the design does not use the full speed of present-day dynamic RAMs, as the three planes are read in parallel during display. In the scheme presented in this paper, the memory is partitioned into segments, three of which store graphics information corresponding to three colours. The three segments are read sequentially within each GDC read cycle, using the full speed of the dynamic RAMs. Moreover, memory segmentation reduces the chip count and PCB area considerably. The system can produce a character display of 40 rows with 64 characters in each row, and can magnify any part of the display by a factor of up to 16.

A new two-dimensional graphics modeling program which has been fully implemented is introduced. Features include a generalized extendable graphics editor, an open-ended library of elements, a translator -macro processor for interface with a wide range of analysis routines, and on-line operating system control.