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Quantum error correction lies at the heart of building reliable quantum information processing systems. Stabilizer codes, a fundamental class of quantum errorcorrecting codes, play a pivotal role in mitigating the adverse effects of noise and decoherence in quantum systems. This paper introduces a novel construction of quantum stabilizer codes using Hadamard difference sets, an elegant mathematical concept derived from combinatorial design theory. In this paper, the construction of the quantum stabilizer codes over non- cyclic Hadamard difference sets with parameters (4m²,2m²-m, m²-m), where m is a positive integer is discussed. Firstly, the parity check matrices are constructed from the Circulant permutation matrices with the help of Hadamard difference sets and then, the Symplectic inner product condition for Hadamard difference sets over binary operation for parity check matrices are obtained to affirm the commutative condition for Stabilizer operators which is vital for the error detection. For application, we constructed a Hadamard difference sets with parameters (16,6,2) for m = 2 of ordered pair of the group Z2 Z8 × (non-cyclic group) and quantum stabilizer codes are obtained by parity-check matrix. [ABSTRACT FROM AUTHOR]

A column‐weight k$k$ LDPC code with the parity‐check matrix H$H$ is called decomposable if there exists a permutation π$\pi$ on the rows of H$H$, such that π(H)${\pi }(H)$ can be decomposed into k$k$ column‐weight one matrix. In this paper, some variations of edge coloring of graphs are used to construct some column‐weight three decomposable LDPC codes with girths at least six and eight. Applying the presented method on several known classes of bipartite graphs, some classes of column‐weight three decomposable LDPC codes are derived having flexibility in length and rate. Interestingly, the constructed parity‐check matrices based on the proper edge coloring of graphs can be considered as the base matrix of some high rate column‐weight three quasi‐cyclic (QC) LDPC codes with maximum‐achievable girth 20. The paper also leads to a simple characterization of elementary trapping sets of the decomposable codes based on the chromatic index of the corresponding normal graphs. This characterization corresponds to a simple search algorithm finds all possible existing elementary trapping sets in a girth‐6 or girth‐8 column‐weight 3 LDPC code which are layered super set of a short cycle in the Tanner graph of the code. Simulation results indicate that the QC‐LDPC codes with large girths lifted from the constructed base matrices have good performances over AWGN channel. [ABSTRACT FROM AUTHOR]

In this paper, we construct new types of codes, called Weighted Block-wise Burst Error Correcting Codes (Weighted BBEC Codes), which are an improvement on the previously known block wise burst error correcting codes in the sense of their weight, i.e., (n = n1 + n2, k) linear codes that correct all the bursts of length b1 (fixed) with the weight w1(w1 ≤ b1) or more (less) in the first sub-block of length n1 and all the bursts of length b2 (fixed) with the weight w2 or more (less) in the next sub-block of length n2. [ABSTRACT FROM AUTHOR]

A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication. [ABSTRACT FROM AUTHOR]

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A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]

This paper presents a joint source–channel image transmission model based on a modified trellis construction using variable-length and fixed-length codes. The model employs linear block trellis codes and a modified Bahl–Cocke–Jelinek–Raviv algorithm for decoding in the source channel. Additionally, this model utilizes a hierarchical tree and a parity-check matrix to combine the source and channel codes, reducing errors in the decoding process and enabling the decoding of longer sequences without substantial loss of quality. [ABSTRACT FROM AUTHOR]

Nested linear coding is a widely used technique in wireless communication systems for improving both security and reliability. Some parameters, such as the relative generalized Hamming weight and the relative dimension/length profile, can be used to characterize the performance of nested linear codes. In addition, the rank properties of generator and parity-check matrices can also precisely characterize their security performance. Despite this, finding optimal nested linear secrecy codes remains a challenge in the finite-blocklength regime, often requiring brute-force search methods. This paper investigates the properties of nested linear codes, introduces a new representation of the relative generalized Hamming weight, and proposes a novel method for finding the best nested linear secrecy code for the binary erasure wiretap channel by working from the worst nested linear secrecy code in the dual space. We demonstrate that our algorithm significantly outperforms the brute-force technique in terms of speed and efficiency. [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10-10 at 3.5 dB Eb/N0 than conventional LDPC codes, which showed a BER of 10-7 at 3 dB Eb/N0. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10-6 at 4.2 Eb/N0 was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10 − 6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving. [ABSTRACT FROM AUTHOR]

In this article, a graph-theoretic method (taking advantage of constraints among sets associated with the corresponding parity-check matrices) is applied for the construction of a double low-density parity-check (D-LDPC) code (also known as LDPC code pair) in a joint source-channel coding (JSCC) system. Specifically, we pre-set the girth of the parity-check matrix for the LDPC code pair when jointly designing the two LDPC codes, which are constructed by following the set constraints. The constructed parity-check matrices for channel codes comprise an identity submatrix and an additional submatrix, whose column weights can be pre-set to be any positive integer numbers. Simulation results illustrate that the constructed D-LDPC codes exhibit significant performance improvement and enhanced flexible frame length (i.e., adaptability under various channel conditions) compared with the benchmark code pair. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of a low-complex iterative symbol-level decoding scheme for Reed-Solomon codes. Most soft-decision iterative decoders for Reed-Solomon codes work on a bit level due to the efficient passing of soft information due to the sparsity of the binary parity check matrix. These decoders yield a good error correction performance, but this comes at the cost of an increased computational complexity resulting from working at a bit-level. This study aims to lower the computational complexity of iterative decoding of Reed-Solomon codes by introducing a high-performance soft-decision iterative Reed-Solomon decoder that works on a symbol-level, in contrast to the bit-level implementation used in most iterative Reed-Solomon decoders. The proposed algorithm utilises soft information to decode while applying information set decoding techniques to an extended parity check matrix. The use of the extended parity check matrix provides additional parity check equations which assist the algorithm in determining the correct information set of symbols used in the decoding process. For a given (n , k) Reed-Solomon code, the algorithm converges to a valid codeword by correctly decoding a specified information set of k symbols from the received vector. Simulations run show the proposed algorithm performs favourably when compared to other symbol-level iterative decoders while working at a relatively lower complexity. [ABSTRACT FROM AUTHOR]

Since their rediscovery in the early 1990s, low-density parity-check (LDPC) codes have become the most popular error-correcting codes owing to their excellent performance. An LDPC code is a linear block code that has a sparse parity-check matrix. Cycles in this matrix, particularly short cycles, degrade the performance of such a code. Hence, several methods for counting short cycles in LDPC codes have been proposed, such as Fan’s method to detect 4-cycles, 6- cycles, 8-cycles, and 10-cycles. Unfortunately, this method fails to count all 6- cycles, i.e., ignores numerous 6-cycles, in some given parity-check matrices. In this paper, an improvement of this algorithm is presented that detects all 6-cycles in LDPC codes, as well as in general bipartite graphs. Simulations confirm that the improved method offers the exact number of 6-cycles, and it succeeds in detecting those ignored by Fan’s method.

Abstract The problem of blind phase offset recovery of low density parity-check (LDPC)-coded systems is considered in this paper. We propose a new algorithm of phase offset estimation that involves the computation and maximization of a likelihood difference (LD)-based cost function calculated from the parity-check matrix of the code. We show in this paper that the new cost function has a simplified form compared to another algorithm proposed in the literature and presents similar estimation performance. Mean squared error (MSE) curves show very good performance of the proposed phase offset estimation algorithm, even at low signal-to-noise ratios.

The large number of inexpensive and energy-efficient terminals in IoT systems is one of the emerging elements of the recent landscape of information and communication technologies. IoT nodes are usually embedded systems with limited processing power devices and strict requirements on energy consumption. In this paper, we consider the design and implementation of a part of the IoT communication uplink stack, namely the error correction coding scheme, for energy-efficient operation. We examine how an efficient rate-adaptive coding scheme, namely the Raptor-like (RL) quasi-cyclic (QC) subclass of low-density parity check (LDPC) codes, can be applied. We present an encoding algorithm designed for an embedded CPU; a respective QC-RL-LDPC decoding scheme, based on typical LDPC iterative decoding; and a combined design procedure for construction of the QC-RL-LDPC parity check matrices. Next, we conduct experiments to explore the time intervals for implemented encoding and the goodput of the coding system with incremental redundancy. We provide the statistical results by combining the measured energy consumption of the encoder and the simulated radio transmitter energy consumption. We demonstrate the comparison of normalized energy consumption statistics with the fixed-rate LDPC coding case. As conclusion, we note that under an unknown channel corruption level, the short block QC-RL-LDPC code implemented in the CPU can achieve higher energy efficiency per information bit compared to a fixed-rate LDPC code. Future work will include an extension of the work to nonbinary QC-RL-LDPC coding design. [ABSTRACT FROM AUTHOR]

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance t -bit Burst Error Correcting (BEC) codes. Parity check matrices (H) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting t -bit burst errors caused by MCUs. [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for constructing quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC‐LDPC codes. Investigations revealed that the proposed large‐sized QC‐LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10−10 at 3.5 dB Eb/N0 than conventional LDPC codes, which showed a BER of 10−7 at 3 dB Eb/N0. Subsequently, implementation of the proposed QC‐LDPC code in a software‐defined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10−6 at 4.2 dB Eb/N0 was achieved. Then, the performance of the proposed codes based on their encoding–decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed–Solomon codes. [ABSTRACT FROM AUTHOR]

Locally recoverable codes (LRCs) have been introduced as a family of erasure codes that support the repair of a failed storage node by contacting a small number of other nodes in the cluster. Boosted by their applications in distributed storage, LRCs have attracted a lot of attention in recent literature since the concept of codes with locality r was introduced by Gopalan et al. in 2012. Aiming to recover the data from several concurrent node failures, the concept of r-locality was later generalized as (r , δ) -locality by Prakash et al. An (r , δ) -LRCs in which every code symbol has (r , δ) -locality is said to be optimal if it achieves the Singleton-like bound with equality. In present paper, we are interested in optimal (r , δ) -LRCs over small fields, more precisely, over quaternary field. We study their parity-check matrices or generator matrices, using the properties of projective space. The classification of optimal quaternary (r , δ) -LRCs and their explicit code constructions are proposed by examining all possible parameters. [ABSTRACT FROM AUTHOR]

A linear code is called a locally repairable code (LRC) with locality r if one can recover an erased code symbol by accessing at most r other code symbols. Constructions of LRCs have been widely investigated in recent years. In this paper, we give a step forward in this direction. Firstly, we propose a novel concept of perfect LRCs whose size exactly achieves the Hamming-type bound, similar to the perfect codes that achieving the Hamming bound in classical coding theory. By the parity-check matrix approach, we establish some important connections between the existence of LRCs and the existence of some subsets of finite geometry and finite fields with certain properties, respectively. By employing q-Steiner systems and sunflowers in projective geometry and difference sets in finite fields, we obtain two new constructions of perfect LRCs with flexible parameters and present several new constructions of k-optimal LRCs achieving another Hamming-type bound under the integers restriction. Moreover, for fixed q and r, the code lengths of all the q-ary r-LRCs constructed in this paper can be arbitrarily large and the code rates can asymptotically achieve the upper bound r r + 1 . [ABSTRACT FROM AUTHOR]

During the digital transmission of information, errors are bound to occur. The errors may be random or burst errors. In this paper, we have obtained necessary and sufficient conditions for the existence of linear codes over that are capable of correcting -repeated burst errors of length(fixed) and -repeated burst errors of length (fixed) within sub-blocks of unequal lengths. We have also constructed a parity-check matrix for such a code.

This paper studies the blind recognition method of the sparse parity‐check matrices of low‐density parity‐check codes in noncooperative communication, which is critical to the reverse analysis of communication protocols using LDPC codes. In this paper, two improvements are made to the algorithm of Liu Qian et al. (2021) for this problem. Firstly, a Gaussian elimination method based on random column exchange and soft information is proposed to enhance the fault tolerance of the elimination process. Secondly, according to the sparse property of the parity‐check matrices of LDPC codes, a random extraction method is proposed to further improve the fault tolerance of the algorithm, and it is verified theoretically. Finally, simulations verify the superior performance of the algorithm proposed in this paper. [ABSTRACT FROM AUTHOR]

In this paper, codes over the direct product of two finite commutative chain rings are studied. The standard form of the parity-check matrix is determined. The structure of self-dual codes is described. A distance preserving Gray map from the direct product of chain rings to a finite field is defined. Two upper bounds on minimum distance are obtained. [ABSTRACT FROM AUTHOR]

The problem of blind phase offset recovery of low density parity-check (LDPC)-coded systems is considered in this paper. We propose a new algorithm of phase offset estimation that involves the computation and maximization of a likelihood difference (LD)-based cost function calculated from the parity-check matrix of the code. We show in this paper that the new cost function has a simplified form compared to another algorithm proposed in the literature and presents similar estimation performance. Mean squared error (MSE) curves show very good performance of the proposed phase offset estimation algorithm, even at low signal-to-noise ratios. [ABSTRACT FROM AUTHOR]

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s. [ABSTRACT FROM AUTHOR]

For the identification of Reed‐Solomon (RS) codes, the existing methods need to test the possible codeword length and the primitive polynomials exhaustively. Exhaustive search leads to high computational complexity. To overcome this limitation and fulfill the requirement in practice, a fast blind identification method is proposed. Different with most methods, our identification method is discussed in Galois Field of 2. First, by using Gaussian elimination, the bit matrix is transformed to the simplest upper triangular form. If the assumed codeword length is right, the matrix is of deficient rank, and the parameters of an RS code can be estimated according to the rank. The null space of the matrix, defined as the equivalent binary parity check matrix, can also be obtained from the simplification result. Then, a candidate set of primitive polynomials is constructed according to the estimated codeword length. By using the matrix null space, the correctness of a candidate primitive polynomial is tested through matrix analysis. Finally, by combining the estimated parameters, the generator polynomial of an RS code is identified. To decrease the bit errors in the matrix, soft‐decision data is used to select reliable bits. Experimental results show the effectiveness and robustness of our method. [ABSTRACT FROM AUTHOR]

New constructions for moderate-density parity-check (MDPC) codes using finite geometry are proposed. We design a parity-check matrix for the main family of binary codes as the concatenation of two matrices: the incidence matrix between points and lines of the Desarguesian projective plane and the incidence matrix between points and ovals of a projective bundle. A projective bundle is a special collection of ovals which pairwise meet in a unique point. We determine the minimum distance and the dimension of these codes, and we show that they have a natural quasi-cyclic structure. We consider alternative constructions based on an incidence matrix of a Desarguesian projective plane and compare their error-correction performance with regards to a modification of Gallager's bit-flipping decoding algorithm. In this setting, our codes have the best possible error-correction performance after one round of bit-flipping decoding given the parameters of the code's parity-check matrix. [ABSTRACT FROM AUTHOR]

Considering the high compression requirements of transmission, lossy block codes are particularly concerned due to their good compression performance and simple implementation. This paper investigates and analyzes the distortion rate performance of protograph LDPC (P-LDPC) codes for Bernoulli sources over AWGN channels. We first analytically establish the connection between the parity check matrix of a P-LDPC code and the extra distortion caused by the noisy channels. It was found that the additional distortion related to channel noise increases with the rising total degree of a parity check matrix. Further, two design algorithms are proposed for optimizing lossy multirate P-LDPC codes, considering the effect of noisy channels. Finally, simulation results demonstrate the robustness of the optimized P-LDPC codes over noisy channels. [ABSTRACT FROM AUTHOR]

We present two lower bounds on sub-packetization level $\alpha $ of MSR codes with parameters $(n, k, d=n-1, \alpha)$ where $n$ is the block length, $d$ is the number of helper nodes contacted during single-node repair, $\alpha $ the sub-packetization level and $k\alpha $ the scalar dimension. The first bound we present is for any MSR code and is given by $\alpha \ge e^{\frac {(k-1)(r-1)}{2r^{2}}}$. The second bound we present is for the case of optimal-access MSR codes and the bound is given by $\alpha \ge \min \left\{{ r^{\frac {n-1}{r}}, r^{k-1} }\right\}$. There exist optimal-access MSR constructions that achieve the second sub-packetization level bound with an equality making this bound tight. We also prove that for an optimal-access MSR code to have optimal sub-packetization level under the constraint that the $\beta $ scalar symbol indices we access from a given helper node is dependent only on the index of the failed node, it is necessary that the support of the parity-check matrix be the same as the support structure of the existing MSR constructions in literature such as the Clay code. [ABSTRACT FROM AUTHOR]

This paper presents a unifying framework to construct low-density parity-check (LDPC) codes with associated Tanner graphs of desired girth. Towards this goal, we highlight the role that a certain square matrix that appears in the product of the parity-check matrix with its transpose has in the construction of codes with graphs of desired girth and further explore it in order to generate the set of necessary and sufficient conditions for a Tanner graph to have a given girth between 6 and 12. For each such girth, we present algorithms to construct codes of the desired girth and we show how to use them to compute the minimum necessary value of the lifting factor. For girth larger than 12, we show how to use multi-step graph lifting methods to deterministically modify codes in order to increase their girth. We also give a new perspective on LDPC protograph-based parity-check matrices by viewing them as rows of a parity-check matrix equal to the sum of certain permutation matrices and obtain an important connection between all protographs and those with variable nodes of degree 2. We also show that the results and methodology that we develop for the all-one protograph can be used and adapted to analyze the girth of the Tanner graph of any parity-check matrix and demonstrate how this can be done using a well-known irregular, multi-edge protograph specified by the NASA Consultative Committee for Space Data Systems (CCSDS). Throughout the paper, we exemplify our theoretical results with constructions of LDPC codes with Tanner graphs of any girth between 6 and 14 and give sufficient conditions for a multi-step lifted parity-check matrix to have girth between 14 and 22. [ABSTRACT FROM AUTHOR]

The bit error rate (BER) performance of spatial modulation (SM) can be further improved by applying quasi-cyclic low-density parity-check (QC-LDPC) codes recommended in 5G to SM. It motivates us to propose a QC-LDPC coded SM (QC-LDPCC-SM) scheme, where SM signals are protected by QC-LDPC codes. To estimate the channel state information at the receiver, a novel iterative joint channel estimation and data detection based on variable block length (IJCEDD-VBL) for SM is presented. In standard 5G LDPC codes, the parity-check matrix contains multiple submatrices, and then we can construct two different QC-LDPC codes by suitably selecting the submatrices. Thus, the QC-LDPCC-SM scheme can be effectively extended to cooperative scenarios when deploying the generated LDPC codes at the source and relay, respectively. We develop an analytical approach for the BER performance of the proposed schemes. The simulation and theoretical results are in good agreement at high signal-to-noise ratio (SNR). Furthermore, the proposed coded cooperative scheme outperforms its corresponding non-cooperative counterpart and the existing scheme. The numerical results also validate the effectiveness of the proposed channel estimation scheme. [ABSTRACT FROM AUTHOR]

The traditional definition of Integrated Interleaved (II) codes generally assumes that the component nested codes are either Reed-Solomon (RS) or shortened Reed-Solomon codes. By taking general classes of codes, we present a recursive construction of Extended Integrated Interleaved (EII) codes into multiple layers, a problem that brought attention in literature for II codes. The multiple layer approach allows for a hierarchical scheme where each layer of the code provides for a different locality. In particular, we present the erasure-correcting capability of the new codes and we show that they are ideally suited as Locally Recoverable codes (LRC) due to their hierarchical locality and the small finite field required by the construction. Properties of the multiple layer EII codes, like their minimum distance and dimension, as well as their erasure decoding algorithms, parity-check matrices and performance analysis, are provided and illustrated with examples. Finally, we will observe that the parity-check matrices of high layer EII codes have low density. [ABSTRACT FROM AUTHOR]

Although long polar codes with successive cancellation decoding can asymptotically achieve channel capacity, the performance of short blocklength polar codes is far from optimal. Recently, Arıkan proposed employing a convolutional pre-transformation before the polarization network, called polarization-adjusted convolutional (PAC) codes. In this paper, we focus on improving the performance of short PAC codes concatenated with a cyclic redundancy check (CRC) outer code, CRC-PAC codes, since error detection capability is essential in practical applications, such as the polar coding scheme for the control channel. We propose an enhanced adaptive belief propagation (ABP) decoding algorithm with the assistance of CRC bits for PAC codes. We also derive joint parity-check matrices of CRC-PAC codes suitable for iterative BP decoding. The proposed CRC-aided ABP (CA-ABP) decoding can effectively improve error performance when partial CRC bits are used in the decoding. Meanwhile, the error detection ability can still be guaranteed by the remaining CRC bits and adaptive decoding parameters. Moreover, compared with the conventional CRC-aided list (CA-List) decoding, our proposed scheme can significantly reduce computational complexity, to achieve a better trade-off between the performance and complexity for short PAC codes. [ABSTRACT FROM AUTHOR]

Let A be a ring with identity, σ a ring endomorphism of A that maps the identity to itself, δ a σ -derivation of A , and consider the skew-polynomial ring A X ; σ , δ . When A is a finite field, a Galois ring, or a general ring, some fairly recent literature used A X ; σ , δ to construct new interesting codes (e.g., skew-cyclic and skew-constacyclic codes) that generalize their classical counterparts over finite fields (e.g., cyclic and constacyclic linear codes). This paper presents results concerning monic principal skew codes, called herein monic principal f , σ , δ -codes, where f ∈ A X ; σ , δ is monic. We provide recursive formulas that compute the entries of both a generator matrix and a control matrix of such a code C. When A is a finite commutative ring and σ is a ring automorphism of A , we also give recursive formulas for the entries of a parity-check matrix of C. Also, in this case, with δ = 0 , we present a characterization of monic principal σ -codes whose dual codes are also monic principal σ -codes, and we deduce a characterization of self-dual monic principal σ -codes. Some corollaries concerning monic principal σ -constacyclic codes are also given, and a good number of highlighting examples is provided. [ABSTRACT FROM AUTHOR]

A block code is called a locally recoverable code (LRC for short) with $(r,\delta)$ -locality, if subject to any $\delta -1$ erasure failures, every symbol in the encoding can still be recovered by accessing at most $r$ other symbols. Recently, it was discovered by several authors that a $q$ -ary optimal $(r,\delta)$ -LRC, i.e., an LRC achieving the generalized Singleton-type bound, can have length much bigger than $q+1$. This is quite different from the classical $q$ -ary MDS codes where it is conjectured that the code length is upper bounded by $q+1$ (or $q+2$ for some special cases). In this paper, we further investigate constructions of optimal $(r,\delta)$ -LRCs along the line of using parity-check matrices. Inspired by classical Reed-Solomon codes and the work in Jin (2019), we equip parity-check matrices with the Vandermonde structure. It turns out that a parity-check matrix with the Vandermonde structure that produces an optimal LRC must obey certain disjoint property for subsets of $\mathbb {F}_{q}$. We manage to show the existence of these disjoint subsets. Thus, this yields an optimal $(r,\delta)$ -LRC with code length $\Omega \left({q^{\frac {\delta }{2}\left({1+\frac {1}{\lfloor \frac {d-1}{\delta }\rfloor -1}}\right)}}\right)\vphantom {\bigg)_{j}}$ , where $d$ is the minimum distance. In particular, to our surprise, for $\delta =2$ this disjoint condition is equivalent to a well-studied problem in extremal graph theory. With the help of extremal graph theory, we succeed to improve all of the best known results in Guruswami et al. (2018) for $d\geq 7$. In addition, for $d=6$ , we are able to remove the constraint required in Jin (2019) that $q$ is even. [ABSTRACT FROM AUTHOR]

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]

We propose a novel approach to optimization of irregular nonbinary (NB) quasi-cyclic (QC)-LDPC codes over small alphabets. In this approach, first, the base parity-check matrices are constructed by a simulated annealing method, and then these matrices are labeled by the field elements while maximizing the so- called generalized girth of the Tanner graph. In order to analyze the performance of the constructed irregular NB LDPC codes, a new ensemble of irregular NB LDPC codes over the extensions of the binary Galois field is introduced. A finite-length random coding bound on the error probability of the maximum-likelihood (ML) decoding over the binary phase shift keying (BPSK) input AWGN channel for the new code ensemble is derived. The frame error rate (FER) performance of the sum-product belief-propagation (BP) decoding of the constructed NB QC-LDPC block codes is compared to that of both the optimized binary QC-LDPC block codes in the 5G standard and the best known NB QC-LDPC codes as well as to the derived random coding bound on the ML decoding error probability. It is shown that the obtained bound predicts the behavior of BP decoding performance of practical NB QC-LDPC codes more accurately than the BP decoding thresholds do. [ABSTRACT FROM AUTHOR]

Syndrome-Trellis Code (STC) is a near-optimal convolutional method for adaptive steganography. Hitherto, the existing adaptive steganography commonly depends on the carefully designed distortion cost function, which controls the embedding position of the message in the cover signal. From another point of view, we implement adaptive steganography by improving the STC coding process (named Adaptive-STC). The parity-check matrix is the key to the encoding and extraction process of STC. In this work, we prove that the average embedding change probability of corresponding elements can be changed by adjusting its submatrix. Following that, we specially design an adaptive parity-check matrix to replace the designed distortion cost to restrict the embedding position. The generation of the adaptive parity-check matrix can be formulated as a multi-constrained integer programming problem in which the width of the submatrix is allocated at a fixed height. To solve this particular problem, we propose a targeted intelligent optimization algorithm (named GOAS) that can adaptively generate the parity-check matrix according to different audio cover. The experimental results show that the proposed method outperforms the state-of-the-art adaptive steganography with reduced embedding changes and improved audio quality while ensuring the ability against steganalysis.

Reed-Solomon (RS) codes are used in many storage systems for failure recovery. In popular software implementations, RS codes are defined by using a parity check matrix that is either a Cauchy matrix padded with an identity or a Vandermonde matrix. The encoding complexity can be reduced by searching for a Cauchy matrix that has a smaller number of ‘1's in its bit matrices or exploiting Reed-Muller (RM) transform in the Vandermonde matrix multiplication. This article proposes two new approaches that improve upon the previous schemes. In our first approach, different constructions of finite fields are explored to further reduce the number of ‘1's in the bit matrices of the Cauchy matrix and a new searching method is developed to find the matrices with minimum number of ‘1's. Our second approach defines RS codes using a parity check matrix in the format of a Vandermonde matrix concatenated with an identity matrix so that the multiplication with the inverse erasure columns in the encoding is eliminated and the decoding can be carried out using simplified formulas. The Vandermonde matrix in such an unconventional RS code definition needs to be constructed using finite field elements in non-consecutive order. A modification is also developed in this article to enable the application of the RM transform in this case to reduce the matrix multiplication complexity. For 4-erasure-correcting RS codes over $GF(2^8)$ G F (2 8) , the two proposed approaches increase the encoding throughput by 40 and 15 percent on average over the prior works based on Cauchy matrix and Vandermonde matrix with RM transform, respectively, for a range of codeword length. Moreover, the decoding throughput is also significantly improved. [ABSTRACT FROM AUTHOR]

An end-to-end joint source–channel (JSC) encoding matrix and a JSC decoding scheme using the proposed bit flipping check (BFC) algorithm and controversial variable node selection-based adaptive belief propagation (CVNS-ABP) decoding algorithm are presented to improve the efficiency and reliability of the joint source–channel coding (JSCC) scheme based on double Reed–Solomon (RS) codes. The constructed coding matrix can realize source compression and channel coding of multiple sets of information data simultaneously, which significantly improves the coding efficiency. The proposed BFC algorithm uses channel soft information to select and flip the unreliable bits and then uses the redundancy of the source block to realize the error verification and error correction. The proposed CVNS-ABP algorithm reduces the influence of error bits on decoding by selecting error variable nodes (VNs) from controversial VNs and adding them to the sparsity of the parity-check matrix. In addition, the proposed JSC decoding scheme based on the BFC algorithm and CVNS-ABP algorithm can realize the connection of source and channel to improve the performance of JSC decoding. Simulation results show that the proposed BFC-based hard-decision decoding (BFC-HDD) algorithm (ζ = 1) and BFC-based low-complexity chase (BFC-LCC) algorithm (ζ = 1, η = 3) can achieve about 0.23 dB and 0.46 dB of signal-to-noise ratio (SNR) defined gain over the prior-art decoding algorithm at a frame error rate (FER) = 10 − 1 . Compared with the ABP algorithm, the proposed CVNS-ABP algorithm and BFC-CVNS-ABP algorithm achieve performance gains of 0.18 dB and 0.23 dB, respectively, at FER = 10 − 3 . [ABSTRACT FROM AUTHOR]

Low-density parity-check (LDPC) codes are known to be one of the best error-correction coding (ECC) schemes in terms of correction performance. They have been utilized in many advanced data communication standards for which the codecs are typically implemented in custom integrated circuits (ICs). In this paper, we present a research work that shows that the LDPC coding scheme can also be applied in a system characterized by highly limited computational resources. We present a microcontroller-based application of an efficient LDPC encoding algorithm with efficient usage of memory resources for the code-parity-check matrix and the storage of the results of auxiliary computations. The developed implementation is intended for an IoT-type system, in which a low-complexity network node device encodes messages transmitted to a gateway. We present how the classic Richardson–Urbanke algorithm can be decomposed for the QC-LDPC subclass into cyclic shifts and GF(2) additions, directly corresponding to the CPU instructions. The experimental results show a significant gain in terms of memory usage and decoding timing of the proposed method in comparison with encoding with the direct parity check matrix representation. We also provide experimental comparisons with other known block codes (RS and BCH) showing that the memory requirements are not greater than for standard block codes, while the encoding time is reduced, which enables the energy consumption reduction. At the same time, the error-correction performance gain of LDPC codes is greater than for the mentioned standard block codes. [ABSTRACT FROM AUTHOR]

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev.14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab.73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability. [ABSTRACT FROM AUTHOR]

A large class of MDS linear codes is constructed. These codes are endowed with an efficient decoding algorithm. Both the definition of the codes and the design of their decoding algorithm only require from Linear Algebra methods, making them fully accessible for everyone. Thus, the first part of the paper develops a direct presentation of the codes by means of parity-check matrices, and the decoding algorithm rests upon matrix and linear maps manipulations. The somewhat more sophisticated mathematical context (non-commutative rings) needed for the proof of the correctness of the decoding algorithm is postponed to the second part. A final section locates the Reed-Solomon skew-differential codes introduced here within the general context of codes defined by means of skew polynomial rings. [ABSTRACT FROM AUTHOR]

To provide reliable transmissions with flexible rates for satellite communications, this paper presents a novel method of constructing multi-rate quasi-cyclic low-density parity-check (LDPC) codes. The basic idea is to generate low-rate codes from a high-rate mother code by combining shortening and extending, which ensures that the generated code family owns the same code length, in order to maintain the same frame structure. The code construction involves the design of base matrices and exponent matrices for the designed codes. A progressive row elimination and addition algorithm is proposed for designing the code base matrices from a high rate to low rates. This algorithm leads to the nested and systematic structure of the parity-check matrices, which are desirable for practical implementations of their encoders and decoders, while ensuring the optimal decoding thresholds. In addition, we construct a circulation coefficient matrix based on finite fields and select the optimal rows in this matrix to construct exponent matrices while considering of cycle structures. We demonstrate that the designed codes achieve better performance for all the code rates than the LDPC codes in DVB-S2X standards. In addition, the proposed codes do not exhibit error floors for their block error rates down to 10−5. [ABSTRACT FROM AUTHOR]

Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of E b / N 0 until the BER of 1e−6. [ABSTRACT FROM AUTHOR]

As an important coding scheme in modern distributed storage systems, locally repairable codes (LRCs) have attracted a lot of attentions from perspectives of both practical applications and theoretical research. As a major topic in the research of LRCs, bounds and constructions of the corresponding optimal codes are of particular concerns. In this work, codes with $(r,\delta)$ -locality which have optimal minimal distance w.r.t. the bound given by Prakash et al. are considered. Through parity-check matrix approach, constructions of both optimal $(r,\delta)$ -LRCs with all symbol locality ($(r,\delta)_{a}$ -LRCs) and optimal $(r,\delta)$ -LRCs with information locality ($(r,\delta)_{i}$ -LRCs) are provided. As a generalization of a work of Xing and Yuan, these constructions are built on a connection between sparse hypergraphs and optimal $(r,\delta)$ -LRCs. With the help of constructions of large sparse hypergraphs, the lengths of codes obtained from our construction can be super-linear in the alphabet size. This improves upon previous constructions when the minimal distance of the code is at least $3\delta +1$. As two applications, optimal H-LRCs with super-linear lengths and GSD codes with unbounded lengths are also constructed. [ABSTRACT FROM AUTHOR]

In this paper, a construction of (n , k , δ) LDPC convolutional codes over arbitrary finite fields, which generalizes the work of Robinson and Bernstein and the later work of Tong is provided. The sets of integers forming a (k, w)-(weak) difference triangle set are used as supports of some columns of the sliding parity-check matrix of an (n , k , δ) convolutional code, where n ∈ N , n > k . The parameters of the convolutional code are related to the parameters of the underlying difference triangle set. In particular, a relation between the free distance of the code and w is established as well as a relation between the degree of the code and the scope of the difference triangle set. Moreover, we show that some conditions on the weak difference triangle set ensure that the Tanner graph associated to the sliding parity-check matrix of the convolutional code is free from 2 ℓ -cycles not satisfying the full rank condition over any finite field. Finally, we relax these conditions and provide a lower bound on the field size, depending on the parity of ℓ , that is sufficient to still avoid 2 ℓ -cycles. This is important for improving the performance of a code and avoiding the presence of low-weight codewords and absorbing sets. [ABSTRACT FROM AUTHOR]

This paper proposes a new method for building low-density-parity-check codes, exempt of cycle of length 4, based on a circulant permutation matrix, which needs very little memory for storage it in the encoder and a dual diagonal structure is applied to guarantee that parity check bits can be recursively computed with linear calculation complexity. The Bit Error Rate performance of the new low-density-parity-check codes was compared to the uncoded bi-phase-shift-keying over additive-white-gaussian-noise channel. This simulation shows that the proposed codes are very efficient over additive-white-gaussian-noise. The proposed codes ensure a very low encoding complexity and reduce the memory storage required for the parity-check matrix, which can be more easily built than others codes used in channel coding.

In this paper, we study a class of nonbinary LDPC (NBLDPC) codes whose parity-check matrices have column weight 2, called NBLDPC cycle codes. We propose a design framework of 2 , ρ -regular binary quasi-cyclic (QC) LDPC codes and then construct NBLDPC cycle codes of large girth based on circulants and finite fields by randomly choosing the nonzero field elements in their parity-check matrices. For enlarging the girth values, our approach is twofold. First, we give an exhaustive search of circulants with column/row weight ρ and design a masking matrix with good cycle distribution based on the edge-node relation in undirected graphs. Second, according to the designed masking matrix, we construct the exponent matrix based on finite fields. The iterative decoding performances of the constructed codes on the additive white Gaussian noise (AWGN) channel are finally provided. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates. [ABSTRACT FROM AUTHOR]

Self-dual maximum distance separable codes (self-dual MDS codes) and self-dual near MDS (NMDS) codes are very important in coding theory and practice. Thus, it is interesting to construct self-dual MDS or self-dual NMDS codes. In this paper, we not only give parity-check matrices of dual codes of twisted generalized Reed–Solomon codes (TGRS codes) but also present a sufficient and necessary condition of self-dual TGRS codes over F q with q an odd prime. Moreover, we construct several classes of self-dual MDS or self-dual NMDS codes from TGRS codes. [ABSTRACT FROM AUTHOR]