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A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65 nm CMOS technology. It results in 81 dB voltage gain, which is 21 dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8 V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1 V supply. The circuit draws a total static current of 295 μ A and occupies 5000 μ m2 of silicon area. [ABSTRACT FROM AUTHOR]

This paper presents a 65 nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100 mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15 dB reduction in the harmonic distortion for 20 mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108 μ m2 silicon area and consumes 0.43  μ A from a 1.2 V power supply. [ABSTRACT FROM AUTHOR]