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This paper studies the frequency tuning effect on the locking range property of a dual-resonance 3:1 injection-locked frequency divider (ILFD) fabricated in a foundry 0.18 μm BiCMOS process. The ILFD architecture is based on a capacitive cross-coupled oscillator in conjunction with a resistor-degraded dual-resonance resonator for the locking range improvement. At a power consumption of 5.26 mW and at injection power of Pinj = 0 dBm the locking range from the measurement is from 6.2 to 12.6 GHz (68.09%). The frequency tuning range of the free-running ILFD shows a frequency tuning hysteresis effect; at low input power level the locking range shows bipolar locking ranges and at high injection power the locking range is independent of the measured voltage tuning direction. [ABSTRACT FROM AUTHOR]

This research studies the RF performance of a wide locking range divided-by-3 injection-locked frequency divider (ILFD) in BiCMOS process. The newly designed ILFD circuit bases on capacitive cross-coupled oscillator with dual-resonance RLC resonator and uses dual-injection technique. It uses one linear mixer and one non-linear harmonic mixer in the frequency conversion. The power consumption of the ILFD core is 5.6 mW and the locking range is from 6.8 to 11.8 GHz (53.76%) at injection power Pinj = 0 d Bm. Measured tuning range shows the dual-band property without frequency tuning hysteresis and is from 3.73 to 2.69 GHz while varactor control voltage is tuned from 0 to 2 V. [ABSTRACT FROM AUTHOR]

This Letter proposes a divide-by-2 injection-locked frequency divider (ILFD) with a new passive resonator. The ILFD in the 0.18 µm 1P6M CMOS process uses a three-dimensional inductor consisted of three series single-path and multi-path inductors. Measured data shows that the varactor-less divide-by-2 ILFD has wide locking range, low power consumption and occupies a small area of 0.4446 × 0.9198 mm2. [ABSTRACT FROM AUTHOR]

This study describes the design and operation principle of quadrature voltage-controlled oscillator (QVCO) with complementary current-reuse (CR) voltage-controlled oscillators (VCOs). One CR complementary metal-oxide semiconductor (CMOS) VCO consists of a pair of p-type metal-oxide semiconductor field-effect transistors (pMOSFETs) and n-type metaloxide semiconductor field-effect transistors (nMOSFETs), and an inductor. The other CR VCO consists of a pair of pMOSFET and heterojunction bipolar transistors (HBTs), and one inductor. The two CR VCOs are used to construct differential VCOs, which are subsequently used to build QVCOs coupled via coupling networks. The Bipolar-CMOS (BiCMOS) VCO and QVCO have been implemented with the Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 0.18 ìm SiGe BiCMOS technology. The CMOS QVCOs have been implemented with the TSMC 0.18 ìm CMOS process. The quadrature phase generation and oscillation frequency equations are derived based on the block diagram of QVCO circuit. [ABSTRACT FROM AUTHOR]

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13-μm CMOS 1P8M process. The designed circuit topology is an n-core LC-tank VCO with an LC resonator. At the supply voltage of 1.1 V, the output phase noise of the VCO is -113.8 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 11.73 GHz and the figure of merit is -192.01 dBc/Hz. The core power consumption is 1.83 mW. Tuning range is 1.47 GHz from 10.66 to 12.13 GHz, while the control voltage was tuned from 0 to 1.2 V. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2170–2173, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25466 [ABSTRACT FROM AUTHOR]

A fourth-order resonator has been implemented to design a 65 GHz injection-locked frequency divider (ILFD) implemented in a 90 nm CMOS process.The ILFD is realized with a cross-coupled nMOS LC-tank oscillator with an inductor switch for frequency band selection. The LC tank can be a second-or fourth-order resonator depending upon the on/off state of a switch across a series-tuned inductor. Measurement results show that at the supply voltage of 0.5 V, the free-running frequency is from 8.68 (16.147) to 9.928 (17.89) GHz for the low- (high-) frequency band. The divide-by-2 operational locking range is from 14.9 (30.64) to 22.2 (37.74) GHz for the low-(high)-frequency band. The divide-by-4 operational locking range is from 34.4 (64.6) to 40.35 (67) GHz for the low-(high)-frequency band. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1421–1425, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25217 [ABSTRACT FROM AUTHOR]

This article proposes a CMOS LC-tank injection locked frequency tripler (ILFT) fabricated in 0.13 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFT.The differential input/output ILFT circuit is realized with a first-harmonic injection-locked oscillator (ILO) stacked in series on two transconductance amplifiers used as a third harmonic generator. The first-harmonic ILO with a series-tuned LC resonator amplifies the signal from the third harmonic generated transconductance amplifier. At the supply voltage of 0.75 V, the free-running frequency of the ILO is from 9.14 GHz to 9.40 GHz. At the incident power of 0 dBm, the total locking range is from the incident frequency 2.95 GHz to 3.43 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1107–1110, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25101 [ABSTRACT FROM AUTHOR]

A low-power differential voltage-controlled oscillator (VCO) is proposed and implemented in a 0.18 μm CMOS 1P6M process. It consists of two single-ended Armstrong oscillators via cross-coupled transistors to obtain a differential output. At the supply voltage of 0.6 V, the output phase noise of the differential VCO is -120.02 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 3.85 GHz and the figure of merit is -188.5 dBc/Hz. Total VCO core power consumption is 2.1 mW. Tuning range is about 550 MHz, from 3.81 to 4.36 GHz, whereas the control voltage was tuned from 0 to 2.0 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 116–119, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24864 [ABSTRACT FROM AUTHOR]

A 17 GHz complementary Colpitts voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The drain-body diode of MOSFET is used as the varactor. The VCO consists of two single-ended complementary Colpitts LC-tank VCOs coupled by a pair of capacitors. At the supply voltage of 1.2 V, the output phase noise of the VCO is -108.54 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 17.3 GHz, and the figure of merit is -189.51 dBc/Hz. Total VCO core power consumption is 2.4 mW. Tuning range is about 1 GHz, from 17.4 to 16.4 GHz, whereas the control voltage was tuned from 0 to 0.9 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 38–41, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24818 [ABSTRACT FROM AUTHOR]

This article presents an eight-phase divide-by-4 silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) injection-locked frequency divider (ILFD). The ILFD is based on a four-stage ring oscillator and was fabricated in the 0.35 μm SiGe 3P3M BiCMOS technology. The divide-by-4 function is performed by injecting a signal to the base of the tail HBT. At the supply voltage Vdd of 1.3 V and at the incident power of 0 dBm, the locking range is about 2.55 GHz from the incident frequency 12.7 to 15.25 GHz. The die area is 0.54 × 0.54 mm2. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 201–204, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24887 [ABSTRACT FROM AUTHOR]

This letter presents a new low power and wide-locking range divide-by-2 injection-locked frequency divider (ILFD). The ILFD consists of a new 5.35 GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18 μm CMOS technology and the core power consumption is 5.72 mW at the supply voltage of 0.8 V. The free-running frequency of the QILFD is tunable from 5.24 to 5.55 GHz. At the input power of 0 dBm, the divide-by-2 locking range is from 8.2 to 13.3 GHz as the tuning voltage is biased at 0.8 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the divide-by-2 mode. The phase deviation of quadrature output is about 1.28°. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2420–2423, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24640 [ABSTRACT FROM AUTHOR]

An LC-tank oscillator-based divide-by-3 injection locked frequency divider (ILFD) is proposed and the series-tuned Armstrong ILFD were implemented in the 0.35 μm SiGe 3P3M BiCMOS technology. Measurement results show that when the supply voltage Vdd is biased at 1.2 V, the free-running oscillation frequency of the ILFD is tunable from 1.19 GHz to 1.0 GHz, and at the incident power of 0 dBm, the operation locking range is about 0.65 GHz, from the incident frequency 3.03–3.68 GHz. The core power consumption is 2.05 mW at Vdd = 1.2 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2239–2242, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24517 [ABSTRACT FROM AUTHOR]

An LC-tank injection locked frequency divider (ILFD) is proposed, and the ILFDs with a direct-injection MOSFET and a tail-injection HBT were implemented in the 0.35 μm SiGe 3P3M BiCMOS technology. Measurement results show that when the tuning voltage is tuned from 0 V to 1.8 V, the free-running oscillation frequency of ILFD is tunable from 2.29 GHz to 2.94 GHz, and at the incident power of 0 dBm the divide-by-2/(-4) operation range is from the incident frequency 4.2 to 6.7/(9.06 to 11.96) GHz. The core power consumption is 2.6 mW at Vdd = 1.1 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1970–1973, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24470 [ABSTRACT FROM AUTHOR]

This article presents a CMOS quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two cross-coupled nMOS divide-by-2 injection-locked frequency divider (ILFDs) with a tail transistor, which serves the role of frequency doubler. The output of the tail transistor in one ILFD is injected to the bodies of the nMOSFETs in the other ILFD. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.595 × 0.896 mm2. At the supply voltage of 0.6 V, the total power consumption is 2.4 mW. The free-running frequency of QVCO is tunable from 5.44 to 5.8 GHz as the tuning voltage is varied from 0.0 to 0.6 V. The measured phase noise at 1 MHz frequency offset is -115.62 dBc/Hz at the oscillation frequency of 5.44 GHz and the figure of merit (FOM) of the proposed QVCO is -186.6 dBc/Hz. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1918–1921, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24495 [ABSTRACT FROM AUTHOR]

This article presents an eight-phase low phase noise CMOS voltage controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and adopts two quadrature cross-coupled nMOS-core VCOs injection-locked through the second-harmonic. The VCO operates from 5.1 GHz to 5.5 GHz with 7.54% tuning range. The measured phase noise at 1 MHz offset from 5.1 GHz is about -115.4 dBc/Hz. The power consumption of the VCO core is 7.43 mW at the supply voltage of 1 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1225–1228, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24270 [ABSTRACT FROM AUTHOR]

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 μm CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank VCO, and a drain-connected-to-body MOSFET is used to enhance the VCO performance. At the supply voltage of 1.0 V, the output phase noise of the VCO is -109.66 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 13.64 GHz, and the figure of merit is -187.15 dBc/Hz. Total power consumption is 3.3 mW. Tuning range is about 270 MHz, from 13.63 to 13.9 GHz, while the control voltage was tuned from 0 to 1.0 V.© 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1174–1177, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24282 [ABSTRACT FROM AUTHOR]

This article proposes a new CMOS LC-tank injection locked frequency divider (ILFD) fabricated in a 0.18-μm CMOS process and describes the operation principle of the ILFD. The ILFD circuit is realized with a double cross-coupled CMOS LC-tank oscillator with a symmetric MOS-switched LC resonator. The ILFD can be used as a first-harmonic injection-locked oscillator, divide-by-2 and divide-by-3 frequency divider depending upon the frequency of the injection signal. Measurement results show that at the supply voltage of 1.8 V, the free-running frequency is from 5.12 to 5.64 GHz. The core current and power consumption of the divider are 2.76 mA and 4.97 mW, respectively. At the incident power of 0 dBm, the locking range is from the incident frequency 9.48 to 11.48 GHz (15.04 to 17.12 GHz) in the divide-by-2(3) mode. © 2009 Wiley Pe riodicals, Inc. Microwave Opt Technol Lett 51: 1263–1267, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24312 [ABSTRACT FROM AUTHOR]

A 5.2 GHz, 0.43 V voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two parallel LC resonators in series with the gates of negative differential resistance transistors. At the supply voltage of 0.43 V, the output phase noise of the VCO is -116d Bc/Hz at 1 MHz offset frequency from the carrier frequency of 5.3 GHz, and the figure of merit is -187.8dBc/Hz. Total VCO core power consumption is 1.83 mW. Tuning range is about 710 MHz, from 5.54 to 4.83 GHz, whereas the control voltage was tuned from 0 to 1.2 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1052–1055, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24216 [ABSTRACT FROM AUTHOR]

This article presents a fully integrated 24-GHz divide-by-2 injection-locked frequency divider (ILFD). The circuit was implemented using a standard 90-nm CMOS process. The ILFD consists of a VCO core and injection MOS for injection signal to the resonator. Two injection MOSFETs are in series with the cross-coupled transistors. The measurement results show that at the supply voltage of 1.2 V, the free-running ILFD is tunable from 11.4 to 12.11 GHz. The locking range is from 21.93 to 27.11 GHz. The output phase noise of the locked ILFD is -109.82 dBc/Hz at 10-KHz offset frequency from the 12 GHz. The core power consumption is 4.32 mW at the supply voltage of 1.2 V. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 32–36, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23986 [ABSTRACT FROM AUTHOR]

This article presents a new divide-by-2 injection-locked frequency divider (ILFD). The ILFD consists of a 2.1-GHz top-series quadrature voltage-controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD uses three-dimensional inductor to save chip area and has been implemented with the TSMC 0.18-μm CMOS technology and the core power consumption is 9.36 mW at the supply voltage of 0.9 V. The free-running frequency of the ILFD is tunable from 2.02 to 2.28 GHz. At the input power of -8 dBm, the total divide-by-2 locking range is from 3.6 to 6.05 GHz as the tuning voltage is varied from 0 to 0.9 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the ÷2 mode. The phase deviation of quadrature output is about 0.19°. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2554–2557, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23724 [ABSTRACT FROM AUTHOR]

This study proposes a new low-voltage divide-by-3 CMOS injection locked frequency divider (ILFD) fabricated in a 0.18-μm CMOS process and describes the operation principle of the ILFD. The ILFD circuit is realized with a CMOS dynamic threshold voltage LC-tank voltage-controlled-oscillator (VCO) with two injection MOSFETs. The self-oscillating VCO is injection-locked by third-harmonic input to obtain the division order of three. Measurement results show that at the supply voltage of 0.36 V, the free-running frequency is from 1.015 to 1.093 GHz. At the incident power of -10 dBm, the locking range is from the incident frequency 3.01 to 3.33 GHz. This is the lowest voltage ILFD ever reported in literatures. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1905–1908, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23499 [ABSTRACT FROM AUTHOR]

This article presents a wide locking-range divide-by-3 injection-locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used to extend the locking range and to reduce die area. The CMOS ILFD is based on a voltage-controlled oscillator (VCO) with cross-coupled switching pairs and TAI-C tanks, and was fabricated in the 0.18-μm 1P6M CMOS technology. The divide-by-3 function is performed by injecting differential signal to the gates of two injection MOSFETs with the drains connected to the VCO outputs and with grounded sources. Measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 1.20 to 1.284 GHz, and at the incident power of 4 dBm the locking range is about 1.9 GHz (45.2%), from the incident frequency 3.3 to 5.2 GHz. The core power consumption is 12.96 mW. The die area is 0.45 × 0.513 mm2. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1682–1685, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23458 [ABSTRACT FROM AUTHOR]

This article proposes a 12 GHz low power differential voltage-controlled oscillator (VCO) based on single-ended Colpitts oscillators. The differential VCO uses two single-ended Colpitts VCOs coupled by a pair of pMOS cross-coupled transistors and a transformer inductor. The differential VCO was fabricated in the TSMC 0.18-nm CMOS process, it oscillates from 11.46 GHz to 12.45 GHz, and the power consumption is 2.76 mW at the supply voltage of 1.2 V. The measured phase noise at 1-MHz offset is g110.95 dBc/Hz at the oscillation frequency of 12.42 GHz. The power consumption of the VCO is 2.3 mA when the supplied voltage is 1.2 V. The figure of merit of the VCO is -188.43 dBc/Hz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1389–1392, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23388 [ABSTRACT FROM AUTHOR]

This study proposes a new divide-by-3 CMOS injection locked frequency divider (ILFD) fabricated in a 0.18-μm CMOS process and describes the operation principle of the ILFD. The ILFD circuit is realized with a Hartley CMOS LC-tank oscillator with two injection MOSFETs. The self-oscillating VCO is injection-locked by third-harmonic input to obtain the division order of three. Measurement results show that at the supply voltage of 1.5 V, the free-running frequency is from 3.86 to 4.27 GHz. At the incident power of 6 dBm, the locking range is from the incident frequency 12.13–12.86 GHz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 906–909, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23242 [ABSTRACT FROM AUTHOR]

This letter proposes a divide-by-3 frequency divider employing inductor-over MOS topology to reduce the chip area and chip cost; the divider was fabricated using the 0.35-μm 2P4M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two inductors and varactors. At the supply voltage of 1.6 V, the divider free-running frequency is tunable from 2.17 to 2.43 GHz, and at the incident power of 0 dBm the locking range is about 1.03 GHz (14.9%), from the incident frequency 6.41 to 7.44 GHz. The core power consumption is 15.1 mW. The die area is 0.753 × 0.786 mm2. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 988–992, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23279 [ABSTRACT FROM AUTHOR]

This article presents a wide locking range injection locked frequency divider (ILFD) implemented using a standard 0.18-μm CMOS process. The ILFD consists of a double-cross-coupled VCO and an injection MOS for coupling injection signal to the resonator. At the supply voltage of 1.8 V, the free-running ILFD is tunable from 4.46 to 4.91 GHz. At the injection power of 0 dBm, the locking range of ILFD is tunable from 6.2 to 11 GHz. The percentage of ILFD locking range is 55.8%, which is the highest among similar published LC-tank ILFDs. The phase noise of the ILFD can track with the injection source. The ILFD has been applied to form a quadrature ILFD and an on-chip VCO has been designed to verify the function of the quadrature ILFD. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 806–809, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23193 [ABSTRACT FROM AUTHOR]

This letter proposes a new injection-locked frequency divider (ILFD) with wide locking range and small die area. The proposed CMOS ILFD consists of an injection MOS and an LC tank voltage-controlled oscillator with a cross-coupled switching pair and tunable active inductors. The divide-by-2 ILFD was fabricated in the 0.18-μm 1P6M CMOS technology. At the supply voltage of 1.8 V, the divider free-running frequency is tunable from 1.46 to 2.7 GHz, and at the incident power of -4 dBm the locking range is about 3.4 GHz (79%), from the incident frequency of 2.6 to 6.0 GHz. The core power consumption is 7.2 mW and the die area is 0.383 × 0.379 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 541–544, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23090 [ABSTRACT FROM AUTHOR]

A switched resonator injection-locked frequency divider (ILFD) designed and fabricated using a standard 0.18-μm CMOS process is presented. The designed ILFD consists of double cross-coupled MOS switching pairs that use the current reuse technique to save power dissipation, and a switched LC resonator. The latter is composed of an inductor, a capacitor, and an inductor–MOS–inductor composite in parallel. The gate bias of MOSFET in the switched resonator is used to tune the free running ILFD frequency and extend the locking range of the ILFD. Measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is from 3.8 to 4.5 GHz, and at the incident power of 0 dBm the locking range is from the incident frequency of 7.6 to 9.26 GHz. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 222–225, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23045 [ABSTRACT FROM AUTHOR]

A novel low-power differential Colpitts voltage-controlled oscillator (VCO) is proposed and implemented in a 0.18-μm CMOS 1P6M process. The proposed circuit topology consists of two single-ended Colpitts LC-tank VCOs, and the differential VCO is obtained by using a cross-coupled nMOS pair. At the supply voltage of 1.8 V, the output phase noise of the VCO is -120.56 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 3.64 GHz, and the figure of merit is -185.9 dBc/Hz. Total power consumption is 3.8 mW. Tuning range is about 487 MHz, from 3.64 to 3.15 GHz, while the control voltage was tuned from 0 to 1.8 V. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 153–156, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23003 [ABSTRACT FROM AUTHOR]

This article presents a divide-by-3 CMOS injection locked frequency divider (ILFD) fabricated in a 0.18um CMOS process. The ILFD circuit is realized with a complementary Colpitts CMOS LC-tank oscillator with an injection MOS connected between the voltage controlled oscillator (VCO) output and ground. The self-oscillating VCO is injection-locked by third-harmonic input to obtain the division order of three. Measurement results show that at the supply voltage of 1.8 V, the free-running frequency is from 2.63 to 3.29 GHz. At the incident power of -6.5 dBm, the locking range is from the incident frequency 8.84 to 9.90 GHz. At the supply voltage of 1.8 V, the core power consumption is 3.06 mW. The chip area is 0.972 × 0.574 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 259–263, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23036 [ABSTRACT FROM AUTHOR]

This article proposes techniques for improving locking range of divide-by-4 injection locked frequency divider (D4ILFD). Two D4ILFDs were designed and implemented. One D4ILFD is made of tapped resonator; the other ILFD is made of switched resonator. Both circuits use a complementary CMOS LC-tank oscillator and are based on the direct injection topology. The wideband function of switched resonator D4ILFD is obtained by tuning the switch across the tank inductors and the varactors. At the supply voltage of 1.8 V and at the incident power of 0 dBm, the locking range of switched resonator D4ILFD is from 7.11 to 9.4 GHz. At the supply voltage of 1.2 V and at the incident power of 0 dBm, the locking range of the tapped inductor D4ILDS is from 7.39 to 9.44 GHz. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1533–1536, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22481 [ABSTRACT FROM AUTHOR]

This paper presents a new differential CMOS voltage controlled oscillator (VCO). The topology of the proposed differential VCO is a combination of Colpitts CMOS VCO and cross-coupled lateral BJT VCO. A symmetric transformer and differential differentially tuned MOS varactors are used to reduce phase noise. The VCO has been fabricated with the 0.18-μm CMOS process. At the 1.2-V supply voltage, the output frequency of VCO is from 5.99 to 6.43 GHz with 441 MHz tuning range and a phase noise of -118.5 dBc/Hz at the 1 MHz offset from the center frequency of 6.43 GHz. Its core current consumption is 2.8 mA and the core power consumption is 3.36 mW. The total power consumption of this VCO is 9.12 mW. The figure of merit (FOM) of this differential VCO is -189.4 dBc/Hz. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 76–79, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22043 [ABSTRACT FROM AUTHOR]

A new circuit technique is proposed to enhance the locking range of divide-by-3 injection-locked frequency dividers (ILFDs) implemented using a standard 0.18 μm CMOS process. The ILFD uses a transformer feedback to increase the second harmonic and enhances the conversion efficiency of injection metal-oxide semiconductor field-effect transistor mixers. The ILFD core consumes 10.8 mW power at the supply voltage of 0.9 V and with a circuit core current of 12 mA. At the incident power of 0 dBm, the measured locking range is 4.2 GHz (37.17%), from the incident frequency 9.2-13.4 GHz. [ABSTRACT FROM AUTHOR]

A balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 μm CMOS 1P8M process.The designed VCO circuit topology is an all nMOS LC-tank Clapp VCO using a series-tuned resonator. At the supply voltage of 0.5 V, the output phase noise of the VCO is -108.69 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 17.72 GHz, and the figure of merit is -186.84 dBc/Hz. The core power consumption is 4.2 mW. Tuning range is about 3.32 GHz, from 17.55 to 20.87 GHz, while the control voltage was tuned from 0 to 1.3 V. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1623–1625, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25275 [ABSTRACT FROM AUTHOR]

This article presents a six-phase silicon-germanium (SiGe) heterojunction bipolar transistor divide-by-3 injection locked frequency divider (ILFD). The ILFD is based on a three-stage differential ring oscillator (voltage controlled oscillators) and was fabricated in the 0.35 μm SiGe 3P3M BiCMOS technology. The divide-by-3 function is performed by injecting a differential signal to the common gates of injection MOSFETs with the drain/sources connected to the VCO outputs. Measurement results show that when the supply voltage Vdd is tuned from 1.4 V to 2 V, the divider free-running oscillation frequency is tunable from 6.2 GHz to 3.58 GHz, and at the incident power of 0 dBm the operation locking range is about 8.3 GHz, from the incident frequency 18.8 to 10.5 GHz. The core power consumption is 8.96 mW at Vdd = 1.4 V. The die area is 0.802 × 0.812 mm2. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1555–1557, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24345 [ABSTRACT FROM AUTHOR]

A new current-reused injection-locked frequency divider is proposed to generate quadrature outputs and implemented using the standard UMC 0.18 μm CMOS 1P6M process. The proposed circuit is made of two LC-tank voltage controlled oscillators (VCOs) stacked in series and the VCOs are coupled with the coupling transistors to generate quadrature signals. The direct injection-locked technique is applied to the VCO to perform a divide by two functions, so that the quadrature circuit can provide low phase noise signal. At the 1.8 V supply voltage, the free running frequency of proposed circuit operates from 2.3 to 2.63 GHz and provides 1 GHz locking from 4.43 to 5.43 GHz. The power consumption is 7.4 mW with 4.1 mA current consumption. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1804–1806, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22604 [ABSTRACT FROM AUTHOR]

A 2.48 GHz class-C voltage controlled oscillator (VCO) without any dynamic back bias circuit is presented. The VCO uses three-path high Q-factor inductor as the low loss resonator and class-C crosscoupled nMOSFET pairs for high dc/RF conversion efficiency and direct cross-coupled pMOSFET for dc current reuse. At the supply voltage of 1.2 V, the core power consumption is 0.24 mW. The phase noise of the VCO is -124 dBc/Hz and the VCO figure of merit is -197.0 dBc/Hz. The VCO was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process and occupies a die area of 0.799 x 0.809 mm2. [ABSTRACT FROM AUTHOR]

A novel wide-locking range divide-by-3 injection-locked frequency divider (ILFD) is designed and fabricated in a standard 0.18 μm CMOS process. The CMOS ILFD uses a class-C capacitive crosscoupled oscillator as the core. It has been found that the locking range of the ILFD is enhanced when the DC-gate bias is smaller than the drain bias in the cross-coupled pair. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. At the incident power of 0 dBm, the maximum locking range is 3.3 GHz (24.17%), from the incident frequency 12-15.3 GHz. At the incident power of 0 dBm, the operation range is 4.8 GHz (37.2%), from the incident frequency 10.5-15.3 GHz. [ABSTRACT FROM AUTHOR]