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Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT ( This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2. These layers grown at T Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry. The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C. We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b. We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs. To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future. [1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021) [2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1

Abstract— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements. Keywords—SmartCut, 3D Integration, Low Temperature, CMOS I. SmartCut Proposal for 3D Sequential Integration In support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4]. In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results. II. Low Temperature SmartCut for 3D Integration For 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed. Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained. III. Low Temperature SOI Performance on Bare Handle wafer The SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut. Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer. Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance. Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated. IV. Conclusion To support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment. V. References [1] J. Macri, Proc. IEEE S3S Conference, 2018 [2] L. Brunet et al., Technical Digest – IEDM Conference, 2018, pp 7.2.1 – 7.2.4 [3] A. Vandooren et al., Proc. IEEE S3S Conference, 2018 [4] C. Fenouillet-Beranger et al., Proc. IEDM Conf., 2014. [5] J. Widiez et al. ECS Trans., 2014, vol. 64(5), pp. 35-48 [6] G. Gaudin et al., ECS J. Solid. State. Sci Tech., 2(12), 2013, pp 534 - 538 Figure 1

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

The paper investigates the stability of the transistor threshold voltage VT with scaling in 30nm High-K/Metal Gate technology. For HfO2 and HfZrO oxides, large VT instability, up to 230mV, is seen when the device width (W) is scaled down to 80nm. It is explained by undesirable lateral oxygen diffusion through the spacers, which mainly modifies the metal workfunction in narrow transistors. HfSiO(N) oxides exhibit a much better immunity to this effect, attributed to a different crystallinity of the HK layer. Moreover, VT stability is not modified by Aluminum incorporation in the gate stack but can significantly be degraded by Lanthanum doping.

3D monolithic integration, also named 3D sequential integration, consists in stacking active device layers on top of each other in a sequential manner. It differs from 3D Packaging where the tiers are fabricated in parallel and then stacked together using a bonding step bonding step (copper to copper or hybrid bonding for example). The monolithic flow offers unique 3D connectivity opportunities: indeed, as the top active patterning is defined by lithography and can be aligned with respect to bottom tiers (alignment marks being seen by transparency), the alignment accuracy and feature size of stacked tiers and inter-tier interconnections are only limited by stepper resolution and not by bonding alignment accuracy like 3D packaging. This allows ultra-high density of 3D vias: state-of-the-art 3D packaging achieves a maximum density of 105 vias/mm2 while 3DSI demonstration using conservative 65nm design rules already achieves a maximum density of 2.107 via/mm2 [1]. However it comes at the cost of thermal budget constraints for top layer processing, as it will be necessary to realize the top tiers without degrading electrical and morphological performances of bottom tiers. In this paper we will review the different fields of application of 3D monolithic integration and describe the related processing options. Furthering Moore’s law for high-performance applications was the original driver for 3D sequential integration. It can be seen at the gate granularity scale, meaning optimizing NMOSfets and PMOSfets independently in two separate layers. This case would offer very fine tuning options on each level (e.g: channel material, strain boosters, substrate orientation, etc.) and avoid costly and complex co-integration steps [2,3]. It can also be seen at the circuit granularity scale by stacking CMOS over CMOS to boost IC speed performance. It can be obtained by reducing the wire length and then the interconnection delay. Performance Power Area (PPA) evaluations have been carried out with various outcomes depending on the application case study, technology node and place and route methodologies [4]. For FPGA (field programmable gate arrays) applications for example, it has been evidenced that 3D sequential integration enables one to reach the PPA of nodes n+1 by stacking 2 n tiers, enabling one to keep following Moore’s law without resorting to straight device scaling [5-7]. Is also important to note that new approaches for “big data” processing such as in-memory and neuromorphic computing require large amounts of on-chip memory with a high density of interconnects between core and memory and 3D Monolithic appears to be an adequate candidate [8]. Maximum thermal budget and technology solutions to realize such integration will be presented. 3D Monolithic can also be very interesting in a Moore than Moore scheme like 3D smart sensors. Lower parasitic capacitance in 3D vias obtained with a monolithic configuration compared to 3D packaging with TSVs could increase data transfer bandwidth. For these sensing applications, analog devices will be needed and depending on their positioning in the 3D stack, may have to be realized with a limited thermal budget. If another tier is realized above they will also need to be resistant to additional thermal budgets. This stability as well as their feasibility with a limited thermal budget must be evaluated. For this latter, technological knowledge on silicides which is usually the first limiting element in thermal budget stability will be presented [9,10]. References : [1] L. Brunet et al., VLSI 2016, [2] P. Batude et al., IEDM 09, [3] P. Batude et al, VLSI 09, [4] M. Jung et al., TCPMT 2015, S. Panth et al., Journal of Information and Communication Convergence Engineering 2014, , [5] O. Turkyilmaz et al., DATE 2014, [6] ITRS 2013, “System driver summary”. http://public.itrs.net, [7] ITRS 2013, “ORTC”. http://public.itrs.net, [8] M. M. Sabry Aly et al., Computer, vol. 48, no. 12 2015, [9] C. Fenouillet-Beranger et al., ESSDERC 2014, [10] C. Fenouillet-Beranger et al., IEDM 2014

Advanced gate stack, with the introduction of high permittivity oxides (mostly Hf-based material) and a metallic gate are widely studied for the future generations of CMOS devices. In particular the integration of new materials as metal gate allows to adjust the threshold voltage of nMOS and pMOS, by changing the material (through work function modulation), the deposition process or the layer thickness [1]. However, such advanced gate stacks have also an impact on the other electrical characteristics, like the channel mobility or the reliability [2]. Correlation between mobility degradation and NBTI has thus been evidenced in advanced highk/metal gate transistors due to nitrogen incorporation originating from the nitrided metal gate or the nitridation of the high-k oxide [2,3]. In this work we have investigated the effect of the metal gate on the electrical properties of MOSFETs, with specific attention to carrier transport. We have brought new experimental results, including low temperature measurements and interface trap characterization, to understand the physical mechanisms which affect the transport.

3D sequential integration of two stacked transistor levels has been recently demonstrated with success on 300 mm wafers with a maximum thermal budget approaching 650°C-20 minutes for the completion of the top level [1]. However, such thermal budget is still too high to avoid any degradation of the bottom transistors performance [2]. Thus, for several technological modules, such as dopant activation, gate stack formation, spacers deposition and source/ drain epitaxy, very low temperature processes must be developed. For low temperature junction activation, solid phase epitaxy regrowth (SPER) is a first option, with typical annealing conditions around 600°C-1 minute [1]. Sub-microsecond laser annealing is a second approach, with the capability to selectively heat a sub-µm surface region. In this paper, we review recent advances in UV pulsed laser annealing in view of 3D sequential integration. Based on 2D numerical simulations, we optimized the process structure for the upper source and drain activation and recrystallization upon laser annealing (wavelength: 308 nm), while trying to avoid any degradation of the bottom transistor. An anti-reflective capping layer over the top transistors is found to reduce laser energy absorption in the upper gate (Figure 1). The lower gate maximum temperature can be reduced down to 600°C (pulse duration: 160 ns) with a structure combining favorable bottom BOX and inter-level SiO2 thicknesses (Figure 2). Moreover, with a shorter laser pulse (80 ns), the bottom level temperature can even approach 500°C while the upper level layers reach 1200°C. To mimic the optimal structures with simple vehicle tests and evaluate the laser annealing process window for dopant activation, SOI structures (25 nm BOX, 23 nm top Si layer) have been implanted with As, BF2 or P, then capped with 30 nm SiN and annealed using SCREEN-LASSE LT-3100 system at various laser energy densities. Sheet resistance measurements combined with SIMS profiles and TEM cross-section observations (Figure 3) allowed us to identify the different regimes encountered as a function of the laser fluence. The process window starts when the whole region amorphized by implantation on top of the single crystalline thin seed layer is melt, and stops with the full SOI layer melt. Around the optimal energy density, we reached perfect crystal recovery and high dopant activation levels, comparable to those obtained with spike RTP. Concerning the laser pulse duration, a trade-off is to be found: The process window is reasonably large in case of a 160 ns pulse and becomes narrower with a 80 ns pulse but such shorter laser treatment is more favorable in terms of heat diffusion. To avoid global routing congestion, the 3D sequential architecture requires the introduction of inter-tier Back-End-Of-line (iBEOL) levels routing the bottom tier. As a consequence, such iBEOL needs to support the thermal budget applied for the top tier processing. Coupling numerical simulations with experimental tests on simplified structures, we investigated the impact of pulsed laser annealing on such inter-level metal interconnection. Based on 28 nm standard design rules, we integrated one metal level (Cu) using porous SiOCH as ultra-low-k dielectric and the appropriate barrier layers. Before submitting such structures to laser annealing, we deposited 50 nm or 120 nm inter-level SiO2 and 20 nm amorphous Si (a-Si) to simulate the top transistor level. According to simulations, above relaxed interconnect regions (large interconnect pitch), the average thermal conductivity of the stack is lower, promoting a slightly faster temperature rise in these regions, compared to more dense regions. A thicker inter-level oxide layer contributes to reduce the peak temperature of the Cu interconnects. Finally, line resistance and lateral capacitance measurements show no modification upon laser annealing, even with conditions leading to the melt of the top a-Si layer, for both 50 and 120 nm inter-level oxides (Figure 4). All these results provide guidelines for low temperature junction formation in a 3D sequential integration using nanosecond laser annealing, reinforcing this technique as a true alternative to SPER. References [1] L. Brunet et al., Proceedings of symposium on VLSI Technology (2016) 7573428. [2] C. Fenouillet-Béranger et al., Proceedings. of Intern. Electron Devices Meeting (2014) 7047121 [3] C. Fenouillet-Béranger et al., Proceedings of SOI-3D-Subthreshold Microelectr. Technol. Unified Conf. (2016) 7804375 [4] P. Acosta-Alba et al., Proceedings of. Ion Implant. Technol. Conf. (2016) [5] S. Kerdilès et al., 16th Intern. Workshop on Junction Technol. (2016) p.72 Figure 1

Low temperature epitaxy is today necessary in thin film Fully Depleted SOI (FDSOI) MOSFETs in order to obtain good quality accesses. Indeed, high temperature process has been shown to be detrimental for the growth of raised sources and drains (RSD) on thin films, as dewetting of the starting film and/or islanding of the epitaxial layer can occur [1]. Besides, low temperature epitaxy is also a key enabler for 3D sequential CoolCubeTM integration, where the 3D fabrication of devices one on top of the other and on the same substrate requires low thermal budget processes (typically T Surface preparation is one of the most critical steps as it directly influences the subsequent epitaxy. Presence of contaminants (C, O, F mostly) can lead to lower growth rates and/or morphological defects in the epitaxial layer. High temperature H2 pre-bake (T>1000°C) yields H-passivated and contaminants-free surfaces, yet it is not compatible with thin films technologies. Nevertheless, native oxide can be removed using a “HF-last” wet clean as well, allowing a reduction in the pre-bake temperature necessary for a good surface preparation (750°C-775°C in [3]). Besides, native oxide can also be removed using the Siconi process, where a NH3/NF3 dry plasma transforms the oxide into a salt which can then be sublimated at temperatures below 200°C [4]. In our work, we show the influence of wet and dry cleans on the quality of the subsequent raised sources and drains epitaxy, the best surface being obtained when using both processes successively (Figures 1a to 1c). Using the optimum wet and dry cleans combination, the thermal budget of the H2 bake could then be reduced from two steps (650°C 2min + 750°C 30s) down to 650°C 2min only. Although higher concentration of interfacial contaminants is to be expected with a lower thermal budget H2 bake, we found no morphological degradation after our standard 650°C epitaxy of SiGe:B raised sources and drains. (Figure 1d). Additionally, equivalent electrical performances were obtained with the lower thermal budget bake (Figure 2). In a second time, the epitaxy temperature was also decreased. High order silanes (e.g. Si3H8, Si5H12) have been proposed to cope with the drastic Si growth rate decrease at low temperatures [5-6]. However, these liquid precursors are very costly, making them less appealing for industrial use. Meanwhile, use of germane (GeH4) and diborane (B2H6) also yields higher growth rates thanks to the preferential desorption of H atoms on B and Ge surface sites. Hence, SiGe:B epitaxy at 500°C was evaluated structurally in a previous work [7]. At such a low temperature, straightforward co-flow selective epitaxial growth (SEG) using chlorinated gases (SiH2Cl2 or HCl) is not possible anymore. Selectivity is then achieved using a deposition/etch (D/E) approach using Si2H6, GeH4 and B2H6 as growth precursors and HCl for the selective etching of polycrystalline materials on dielectrics. Good quality 2D epitaxial layers can thus be obtained with full selectivity over the buried oxide and the nitride gate spacer (Figure 1e). We also show that doubling the number of cycles (i.e. to D/E/D/E strategy) yields smoother access regions, yet at the cost of the selectivity (Figure 1f). Use of more reactive chlorine gas is therefore proposed to obtain desired selectivity at 500°C. Finally, for the first time, pMOSFETs on thin SOI (tSi=11nm) substrate were fabricated using the new 500°C D/E recipe for SiGe:B raised sources and drains and functional transistors were obtained (Figure 3). A thorough electrical analysis of these devices (e.g. access resistance, mobility) will be provided in this work. [1] Y. Ishikawa et al., Appl. Surf. Sci. 90, 11-15, 2002. [2] P. Batude et al., Proceedings of 2015 VLSI Technology Symposium, 48-49, 2015. [3] A. Abbadie et al., Appl. Surf. Sci. 225, 256-266, 2004. [4] M. Labrot et al., Appl. Surf. Sci. 371, 436-446, 2016. [5] A. Gouyé et al., Appl. Phys. Lett. 96, 063102, 2010. [6] J. C. Sturm et al., ECS Trans. 16 (10), 799-805, 2008. [7] J-M. Hartmann et al., ECS J. Sol. State Sci. Technol. 3, 382-390, 2014. Figure 1

Monolithic 3D Integration (3DMI) consists in processing transistors on top of each other sequentially. This technology appears to be an alternative solution to scaling, from the 7nm node integration and below, as substantial gain in area and performance as compared to planar technology is expected without scaling the transistor technology node. 3DMI appears to be the most optimized way to take advantage of the vertical dimension as almost no alignment constraints remains. By using a standard lithography, the top transistors can be aligned directly onto their bottom counterparts with a high accuracy (see Fig. 1), contrary to TSV-based 3D technologies [2]. Furthermore, 3DMI is a highly versatile technology as the different transistor levels can be optimized independently, from the choice of the channel characteristics (e.g. material, orientation, strain) to the architecture itself (e.g. CMOS on CMOS, PMOS on NMOS, FinFET on BULK, LVT on RVT) [3]. Such sequential integration raises two main technological challenges: - Creating an active layer above a bottom transistor which will become the channel of the top transistor. In order to achieve similar performance for top FET than bottom FET, the substrate quality must be equivalent than commercial substrates. Thus, this layer must be monocristalline and defect free in order to optimize the mobility and to be consistent with high performance criteria. A precise thickness control is also necessary in order to avoid device performance dispersion. - Realizing a high performance top transistor level without degrading the bottom level as the stacked transistor levels are processed sequentially, i.e. at low temperature process –typically below 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C [4]. To tackle the first challenge, we transfer a thin silicon layer from a high quality Silicon On Insulator (SOI) wafer by direct bonding. It appears to be the most effective solution to obtain a defect free monocristalline active layer with a well-controlled thickness. This method is preferred to different techniques which have been developed to create large monocristal grains of silicon either by laser anneal of amorphous Poly-Silicon [5] or by µ-Czochralsky process [6]. However, in both cases, large “seed layers” are necessary to control the orientation and the size of these grains, which is not consistent with for high density circuits. For this layer transfer, a blanket SOI wafer on which a Si02 layer is either grown or deposited, is bonded on the classical pre-metal dielectric above the bottom transistor level. The SOI backside is then removed by grinding and chemical etching to keep only the silicon layer. While expert knowledge has been reached for full sheet wafer bonding, the situation on a patterned layer can be really challenging with the design rules of 3DMI. In order to face these challenges, the surface preparation, the direct bonding process and the thinning steps have been optimized to prevent any defect on the whole 300mm surface. Also TMAH bevel edge protection and silicide protection layer have been added. This work will give a general overview of 3D monolithic challenges. Also, a specific focus will be made on direct bonding which is a major enabler of this type of integration. Indeed among the other alternative techniques, it appears to be the best solution to meet the high performance and high density criteria. REFERENCES: [1] P. Batude et al., VLSI Technology, pp. 158 (2011) [1] P. Batude et al., ECS Spring meeting, (16) pp. 47 (2008) [2] P. Batude et al., IITC-AMC (2014) [3] P. Batude et al., IEDM, pp.731-734 (2011) [4] C-H. Shen et al., IEDM, pp. 931-934 (2013) [5] J. Derakhshandeh et al., TED vol.58, no. 11 (2011) Fig.1: 3DMI demonstration with ultra-high alignment between the stacked transistors [1] obtained with 248nm stepper.

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