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The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively. [ABSTRACT FROM AUTHOR]

Inevitability to reduce the size, cost and complexity of multilevel inverter (MLI) to evolve simplified RSC (Reduced switch count) MLIs has created diversified effects such as limited switching redundancies which further restricted modularity and flexibility of implementing PWM schemes. Among the PWM schemes of RSC-MLIs, modified reduced carrier (MRC) PWM with unified switching logic (USL) is the simplest and claims to be superior with the state of art in terms of implementation, line harmonic performance, imposing least controller computational burden (of 6.5 µS to realise a three-phase seven-level RSC-MLI) by adapting minimal carrier constraints. However, this is valid for sophisticated digital controllers such as dSPACE MicroLabBox, but not for low-end cost-effective controllers such as dSPACE1104 (imposing a computational burden of nearly 25 µS to control a single-phase RSC-MLI). Thus, this paper proposes an improved USL which adopts no carrier constraints and operates with less computational burden over the conventional USL. The proposed USL gives flexibility to the user to implement a part of the switching logic with analogue circuits and thereby avoid the requirement of high-end digital controller. The scalability and superiority of the proposed USL is demonstrated for symmetrical and asymmetrical configurations of popular cascaded T-type RSC-MLI. Efficacy of the proposed USL is demonstrated with dSPACE 1104 controller and dSPACE FPGA R&D Micro-lab Box. [ABSTRACT FROM AUTHOR]

Herein, we report the synthesis of a small molecule quinoline Schiff-base "turn-on" fluorescence probe L, denoted as (2-NC9H6)C(H)=N(C6H4OCH3-p), utilizing 4-aminoanisole and quinoline-2-carboxaldehyde as precursors. The synthesized probe was comprehensively characterized through EA,1H/13C NMR, FT-IR, and ESI-MS spectral analysis. In a CH3CN/H2O solution (1/1, v/v, 0.01 M PBS buffer, pH = 7.30), probe L responded to Hg(II) with high sensitivity (LOD = 2.98 × 10−7 M) and selectivity. Upon binding to Hg(II), the fluorescence of the probe shifted from being initially off to a distinct blue emission. The probe L to Hg(II) binding ratio was 1:1 and the binding constant was 1.955 × 104 M−1. The detection mechanism of Hg(II) by probe L is due to the complex formation between the metal ion and imine nitrogen (–CH = N), thus causing chelation-enhanced fluorescence. TD-DFT studies at the B3LYP/6-31G(d) level of theory further confirmed that the complexation of L and Hg(II) occurred. Finally, probe L could reversibly identify Hg(II) upon adding EDTA, thus developing a molecular logic gate. In addition, this probe was successfully used to detect Hg(II) in actual water samples. : [ABSTRACT FROM AUTHOR]

A multilevel inverter performs a major role in increasing the range of the level of output voltage without the use of a transformer in the power sector. Here an asymmetrical 15-level multilevel inverter fed from three unequal voltage sources has been proposed. The various modes of the conduction of the eight switches with the switching pattern are discussed with the circuit's operation. The performance of the circuit is analysed using various techniques under MC-PWM methodologies such as Phase disposition (PD) PWM, Alternate POD (APOD) PWM, and Phase Opposition Disposition (POD) PWM. Key Finding: The logical expression used for generating the pulse pattern of the above techniques using the level shifting PWM technique to reduce the harmonics is performed, simulated, and compared by implementing three techniques for linear and non-linear load. The performance in terms of THD of output voltage under various modulation indexes is compared for various Llvel-shifting techniques. The performance of this 15L-MLI is simulated using MATLAB/Simulink and implemented in a prototype hardware model. [ABSTRACT FROM AUTHOR]

This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed. [ABSTRACT FROM AUTHOR]

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower Ioff current of 4.34 × 10−19 A, an Ion current of 4.17 × 10−06 A with an Ion/Ioff current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices. [ABSTRACT FROM AUTHOR]

Combinational logic circuits (CLCs) are basic building blocks of a system and optimization of these circuits in terms of reduced gates, transistors, or levels will lead to reduced area on chip, reduced power, and improved speed. Simulated annealing (SA) is a thermo-inspired metaheuristic used for solving various engineering and non-engineering problems. SA is also used for the realization and optimization of CLCs. Circuits with a large number of inputs and outputs require more generations for realization. Realization of the optimal circuit with fewer generations is desired as realization time increases with increase in the number of generations. In this paper, an attempt is made to realize circuits using population-based SA with fewer generations. SA with partitioning approach is proposed in this paper for circuits that could not be realized with fewer preset generations. To evaluate the performance of the proposed work, benchmark circuits from LGSynth'91 are considered, and it is observed that the success rate improved and realization time reduced with the proposed partitioning approach. During the evaluation, it is also observed that the gate count was reduced by 2.5–77.39% and the transistor count was reduced by 7.69–95.53% on using proposed work with fewer generations over circuits reported in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a novel circuit technique NSCDH, to construct OR gates with 8 inputs up to 128 inputs and single output, which can be cascaded to further stages. It uses stage isolation technique to provide current free nodal state comparison with the ability to hold circuit at an optimal state, thereby resulting in 44.6% lesser power consumption and 16.1% higher noise immunity at 8 inputs as compared to CDDK (2019) and 24.4% lesser power consumption at 128 inputs as compared to CDDK (2019). Circuit simulation is done using HSpice. Standard BSIM4 90 nm PTM file is used to model NMOS and PMOS transistors. Circuit schematic is made using LT Spice. OR gates built using this technique can be used in many applications as multiplexers, read–write data paths, memories, and adders. [ABSTRACT FROM AUTHOR]

Electric double layer (EDL) gating is a technique in which ions in an electrolyte modulate the charge transport in an electronic material through electrical field effects. A sub-nanogap capacitor is induced at the interface of electrolyte/semiconductor under the external electrical field and the capacitor has an ultrahigh capacitance density (~µF cm−2). Recently, EDL gating technique, as an interfacial gating, is widely used in two-dimensional (2D) crystals for various sophisticated materials characterization and device applications. This review introduces the EDL-gated transistors based on 2D materials and their applications in the field of bioinspired optoelectronic detection, sensing, logic circuits, and neuromorphic computation. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on the computation-in-memory (CIM) architecture are contemplated as the future generation of digital integrated circuits. It overcomes the limitations of von-Neumann architecture by offering solutions to problems such as memory wall and standby power dissipation. In this work, we have developed hybrid logic gates, such as AND/NAND, OR/NOR, and XOR/XNOR, for CIM architecture by integrating three terminal spin-Hall effect assisted spin transfer torque (SHE + STT) MTJs with standard CMOS. To write the MTJs an auto-write-stopping (AWS) circuit is adopted, whereas to perform the logic operations and produce the corresponding outputs, an improved sense amplifier circuit (ISA) is employed. All the hybrid logic gates are investigated for key performance indicators such as power, delay, device count, and power delay product (PDP). The results are compared with their conventional counterparts. The comparison reveals that the ISA + AWS-based hybrid gates dissipate 50.52% lower total power. The worst-case read delay of ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates are 27.41%, 13.4%, and 21.28% lower. Meanwhile, the reduction of read PDP (write PDP) is 47.64% (37.09%), 25.78% (36.29%), and 39.31% (35.48%) observed with ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates in comparison with the conventional counterparts. Hence the ISA + AWS gates are superior in terms of total power dissipation, worst read delay, and read/write PDP. Further, we have conducted Monte-Carlo simulations on all the logic circuits to study the parameter variations during fabrication. [ABSTRACT FROM AUTHOR]

Remanufacturing is the rebuilding of a product to specifications of the original manufactured product using a combination of directly reused, repaired and new parts. Disassembly, the first and arguably most important process in remanufacturing, tends to be labour-intensive due to complexities in the conditions of end-of-life products returned for remanufacture. Robotic disassembly is an attractive alternative to manual disassembly but robotic systems cannot plan disassembly sequences automatically and manual planning is still necessary. Planning requires machines to interpret physical space using a suitable representation to reflect physical contacts and constraints as well as rules for deciding the sequences of disassembly operations. This paper proposes a representation to describe physical contacts and constraints, and a new approach allowing machines to plan disassembly using the representation. The approach involves employing an assembly matrix and simple logic gates to generate a contact matrix, a space interference matrix and a relation matrix. Rules and algorithms are discussed to explain the calculation of sequences through manipulating the three matrices. A key benefit is that the proposed method can deal with interlocked mechanical structures which cannot be handled using conventional methods. The proposed method is also flexible and is suitable for either selective or complete disassembly. [ABSTRACT FROM AUTHOR]

Calculating power and delay in VLSI circuits are two main challenges in designing CMOS VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor domino logic for power and delay reduction. The lector technique uses two leakage-controlled transistors, PMOS and NMOS. The gate terminal of PMOS is connected to the source of NMOS, and the gate terminal of NMOS is connected to the source of PMOS. NMOS transistor N5 is used in the proposed circuit, driven by a dynamic node, which helps to reduce the power. This manuscript uses the proposed technique to design a buffer, two-input – AND gate, OR gate, and XOR gate circuits. The logic gates are simulated on the gpdk 45 nm cadence virtuoso software tool. The simulation result shows that the proposed domino logic circuit significantly reduces power, delay, energy, and leakage current. Monte Carlo analysis is performed to study the mean and standard deviation of the proposed circuit with 1000 samples. [ABSTRACT FROM AUTHOR]

This study explores the critical nexus of communicative capitalism, neurodiverse employment, and DEI in public relations research. Through a critical discourse analysis of the owned and shared media of 13 neurodiversity workforce intermediaries (NWIs), we investigate how NWIs brand neurodiversity and their relationships with their publics against the backdrop of communicative capitalism. Our analysis unearthed power-laden tensions in traditional and novel brandings of neurodiversity, as well as ambivalent orientations that concurrently advocate for social change and economic productivity. We argue that attempts at change empowerment are short circuited by capitalist logics that value only those narrow elements of neurodiversity that fit within a business case for diversity. [ABSTRACT FROM AUTHOR]

This article introduces a new multilevel that is 17-level inverter. This circuit contains 14 switches, 2 diodes, 3 capacitors and a DC source. Each cycle contains 18 steps, including two steps at the zero crossing. Due to the self-polarity nature of the proposed topology, no H-bridge is necessary. The pulse width modulation approach is used to generate gate pulses from logic gates while also balancing the power across the capacitors. A prototype is constructed to experimentally verify the result. The superiority of this topology is demonstrated by comparison with other similar-level topologies. In addition, a diode and an inductor are connected in a way that reduces the short-circuit capacitance current. [ABSTRACT FROM AUTHOR]

Electroactive polymers (EAPs) have the interesting property of generation and flow of charges and possess exciting tunable optoelectronic properties by incorporating side chains via 'grafting' from the backbone chain retaining its properties and importing new properties from the grafted chains. The graft copolymers of EAPs exhibit exciting tunable optoelectronic properties by varying external stimuli like pH, temperature, ions, surfactants, light etc. Grafting of two main electroactive polymers e.g. polythiophene (PT) and poly(vinylidene fluoride) (PVDF) have spurred significant research attention and the controlled grafting has been made using atom transfer radical polymerization (ATRP) technique with suitable catalyst/ligand systems. Few examples of grafting of PT and PVDF by RAFT polymerization are also described. This feature article delineates controlled grafting of different stimuli-responsive polymers on polythiophene and PVDF backbone highlighting their optoelectronic properties, useful for making chemical/biological sensors, logic gates and antifouling/antibacterial membranes. Interactions of the grafted chains with the external physical or chemical stimuli (like pH, temperature, photoirradiation, ions, surfactants, etc.) significantly alter the backbone conformation both in solution and solid state. This leads to changes in conjugation length of the backbone chain, hence tunes the band gap varying the optoelectronic properties useful for fabrication of stimuli dependent sensors and modulation of membrane pore size suitable for antifouling and antibacterial membranes. [ABSTRACT FROM AUTHOR]

This study introduces chromone-based probes designed for selective cyanide ion detection in acetonitrile. Through various spectroscopic methods, the probes demonstrated a colour change from colourless to yellow, enabling naked-eye detection of cyanide ions. The sensors exhibited high sensitivity (6.2 µM) and selectivity for CN¯ ions over common anions. Computational analyses by FMO, NCI, QTAIM, NBO and EDD analysis confirmed the probes' suitability for cyanide detection. Overall, the synthesised compounds present a promising solution for practical applications in the field of cyanide ion sensing. [ABSTRACT FROM AUTHOR]

In this paper, all optical OR, AND, NOR and NAND gates based on linear photonic crystals (LPhCs) have been numerically designed and simulated by the plane wave expansion (PWE) and finite difference time domain (FDTD) methods. The LPhC fundamental structure with cross-section of 114 μ m 2 is used for designing the proposed all optical gates (AOGATEs), which is composed of 15 × 23 cubic matrix of dielectric silicon rods in air substrate. The mechanism of the proposed AOGATEs is performed based on phase shift keying (PSK) technique and beam interference effect. Simulation results by FDTD approach illustrate the minimum contrast ratio of 8.88 and 10.31 dB for all optical AND/NOR and OR/NAND logic gates, respectively. Also, the minimum bit rate is obtained as 3.34 Tb/s for AND/NOR and 5 Tb/s for OR/NAND logic gates. [ABSTRACT FROM AUTHOR]

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13. [ABSTRACT FROM AUTHOR]

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make Cin = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques. [ABSTRACT FROM AUTHOR]

This paper deals with the design and analysis of a new 4-2 compressor which can be used in high-speed multipliers. The proposed compressor features eliminated glitch at the output waveform. By optimum tuning of the width of the transistors, Cout is produced more quickly, and therefore higher operating speeds can be achieved. The effect of process variation on the circuit has been studied and a new structure is proposed to overcome the effect of process variation by utilizing a reference voltage generator circuit. A 32 × 32-bit multiplier has been developed utilizing these compressors in order to evaluate the new compressor in a practical environment. The total multiplier circuit was simulated with HSPICE simulator (BSIM3v3 parameters) using CMOS standard cell library of 0.18 µm and the Layouts were extracted with Cadence Virtuoso v 5.1 Layout Plus tool. The simulation results represent 185 × 10−3 pj Power-Delay-Product (PDP) and 40 pj × ps Energy Delay Product (EDP) with 221 ps delay from input to output. [ABSTRACT FROM AUTHOR]

Fast Fourier Transform (FFT) is widely used in image and video processing applications to convert the respective image or video frames into transform domain that is very helpful to extract the accurate features of that image or video frame for various real-time applications. In this paper, efficient non-separable 8-point FFT architecture (DIT-FFT) is proposed that is implemented on Spartan-6 (xc6slx45-3csg324) FPGA. The proposed architecture consists of Data Format Conversion, Addition, Subtraction, Multiplier Equivalent and D-FF blocks, respectively. The non-separable equations of 8-point DIT-FFT are derived from the respective Butterfly Diagram that is then implemented using basic logic gates, which optimises the hardware utilisations with the help of Complex Conjugate property. The constant multiplications present in the non-separable DIT-FFT equations are implemented through Adders and Shifters presents in Multiplier Equivalent block which further optimises the overall hardware utilisations. Moreover, the Q-format are used to increase the data accuracy of the architecture. The comparison results show that the proposed architecture is better than existing in different prospectives. [ABSTRACT FROM AUTHOR]

This work explores homo- and heterojunction tunnel field-effect transistor (TFET)-based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homojunction TFET-based NAND and NOR logic circuits, it has been observed that NAND consumes less power than the NOR gate since current drawn by PTFET in the pull-up network of the NOR gate is higher. The delay of the homojunction TFET-based NOR logic gate is lower than that of the NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double-gate heterojunction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Heterojunction TFET-based NAND with the pseudo-derived logic circuit shows a lower propagation delay of 103 times and a reduction in power consumption by 0.75 times compared to the heterojunction NAND logic circuit. Heterojunction TFET-based NOR with pseudo-derived logic has the reduction in power consumption of 103 times and lower propagation delay than the heterojunction NOR logic circuit. [ABSTRACT FROM AUTHOR]

This document discusses the challenges and advancements in the design, control, and application of unmanned surface and underwater vehicles (USVs and UUVs). These vehicles are used for tasks in hazardous environments, such as underwater missions. The challenges include uncertain models, nonlinear dynamics, navigation, control, communication, energy efficiency, and power management. The document also provides summaries of six research papers that explore topics such as microgrid systems, underwater target tracking, object detection for search and rescue operations, logic gates in digital circuits, and maintainability analysis of naval ships equipment. The authors express gratitude to the contributors and reviewers for their valuable contributions. [Extracted from the article]

In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit. [ABSTRACT FROM AUTHOR]

The modelling of semi-conductor elements in molecular electronics as an emerging technological field requires further development. Using circuit elements, a typical model is presented in this paper. Taking the advantage of this model, a pyridine derivative molecular diode is modelled and the theory behind the components of the molecule model is explained. Subsequently, the physical properties of the proposed pyridine derivative molecular diode, including the electric potential drop along the molecule, rectification ratio, diode current, power consumption, transmission spectrum, and electron density along the molecular diode, are investigated. Then, using the molecular diode model, the basic logic gates including AND, OR, NOT, and XOR gates are modelled and using the basic gate model, the modelling of basic reversible molecular logic gates including Feynman, Toffoli, BVF, and Peres gates are implemented. Moreover, a full adder is modelled using the two Peres gate model. [ABSTRACT FROM AUTHOR]

In this article, MEMS-based logic gates such as OR, AND, NOT, NOR, and NAND gates with functionalities similar to the electronic digital devices are designed and simulated. The key feature of these logic devices is that the mechanical cantilever structure of the basic piezo-actuator is adapted to operate like a particular digital logic gate based on the digital inputs. Complete analytical modelling for a single piezo-actuator with a correlation between its out-of-plane tip deflection with applied voltage is obtained. The proposed digital logic devices are further validated through simulation using the MEMS CAD tool CoventorWare. [ABSTRACT FROM AUTHOR]

Herein, we have presented a novel bare eye detection method which is based on the anion competing for a metal receptor with a chromogenic indicator. In this essay, there are highly specific interactions among the anions and the metal ions and 4-(2-Pyridylazo) resorcinol (PAR) probe in a competition assay format. The system designing is simple and it is fast in operation so that is promising than other methods because it did not need organic solvents, preparation and separation processes, chemical modification and equipped devices. In this way, Cd2+ and Cu2+ ions were detected by changing colour from yellow to light orange and red, respectively (in aqueous solution), which could be distinguished by naked eyes. The selectivity of these complexes towards anions wassurveyed by competition experiments in the presence of different anions. The obtained results were shownin which there were variations in the UV-Vis spectrum and colour of the solution of the [PAR-Cd2+] in the presence of SO32- and PO43- anions. The high sensitivity and selectivity for phosphate and sulphite were obtained by changing the metal ions. That is, by using Cu2+ instead of Cd2+in the PAR-metal, only SO32- anion was detected and the detection limit of SO32- ion was obtained 1.20 µmol L−1. This novel system has employed for simultaneous determination SO32- and PO43- anions in some real samples by changing the metal ion in the complex. Furthermore, the INHIBIT molecular logic gate was obtained using chemical inputs (Cu2+ and SO32-) and UV-Vis absorbance signals as the output. [ABSTRACT FROM AUTHOR]

Since the first report on truly two-dimensional (2D) magnetic materials in 2017, a wide variety of merging 2D magnetic materials with unusual physical characteristics have been discovered and thus provide an effective platform for exploring the associated novel 2D spintronic devices, which have been made significant progress in both theoretical and experimental studies. Herein, we make a comprehensive review on the recent scientific endeavors and advances on the various engineering strategies on 2D ferromagnets, such as strain-, doping-, structural- and electric fieldengineering, toward practical spintronic applications, including spin tunneling junctions, spin fieldeffect transistors and spin logic gate, etc. In the last, we discuss on current challenges and future opportunities in this field, which may provide useful guidelines for scientists who are exploring the fundamental physical properties and practical spintronic devices of low-dimensional magnets. [ABSTRACT FROM AUTHOR]

Using multi-valued circuits reduce the number of connections on a chip and the area of the chip and power consumption in the connections.. In this paper, a new structure of single-source logic gates, AND, OR and BUFFER were designed using CNFET. In the new design, AND and OR have directly been designed instead of NAND and NOR, because in previous designs, NAND and NOR were needed to achieve AND and OR. Also, due to the fact that PT, NT inverters and positive, negative logic gates have been used, it is possible to adjust the voltage of the switch to achieve a better noise margin. Also, with the proposed ternary BUFFER, a single-source ternary memory cell was designed, with the advantages of a smaller number of transistors and the need for only a single line for reading and writing, which greatly reduces the number of interconnections. Since the number of interconnections in the memory array increases tremendously, this design significantly reduces the number of connections in the memory array. The simulation results using Hspice software and the Stanford CNT-32 nm model indicate the correct operation of the circuits and represent the improved 70% and 90% in PDP of gates compared with the state-of-art work. [ABSTRACT FROM AUTHOR]

The naturally occurring compound andrographolide 1 was used as a substrate for the synthesis of a novel terminal alkyne 3 which on copper(I)-catalyzed azide-alkyne cycloaddition (CuAAC) reaction with azides 4a-l, 7 and 9 furnished a series of regioselective andrographolide triazolyl conjugates 5a-l, 8 and 10, respectively. A free glycoconjugate 6 was also prepared by selective deprotection of compound 5i in good yield. All the compounds were characterized by absorbance, FT-IR, NMR, and HR-MS analyses. The triazolyl conjugate 8 was further investigated as a probe for selective detection of Fe3+ ion in matrix. The mode of attachment of Fe3+ ion to the compound 8 was established by absorbance, fluorescence, infrared (IR), and nuclear magnetic resonance (NMR) spectroscopy, and high resolution mass-spectrometry (HR-MS). The logic gate circuits were constructed for the probe 8 and ethylenediaminetetraacetic acid (EDTA). The environmental perspective of probe 8 was investigated in real water samples. [ABSTRACT FROM AUTHOR]

This paper proposes a new modified level, increased nearest level modulation (NLM) method to improve the THD quality and enhance the quality of output voltage of modular multilevel converters (MMCs). Offshore wind farm links need connections from onshore national grids, and this paper is consistent with higher level voltage generation techniques by using MMC. By changing the on-number sub-modules (SM) at the middle position after using the round function, the generated gate logic by using the proposed method maintains a fixed magnitude value of phase voltage with a maximal number of (2 N + 1) levels, where N is the number of sub-modules per arm. The proposed method maintains the advantages of the conventional NLM such as simple implementation and low switching loss and avoids the disadvantages of the existing NLM method such as capacitor voltage ripple, peak value of arm inductor voltage, complexity in topology, etc. Both the advantages and disadvantages of the proposed and the conventional schemes are also studied, and an illustrated comparison shows the THD result differences for four methods. The system is simulated using MATLAB-Simulink to validate the feasibility of the proposed scheme and carried out by a hardware-in-the-loop simulation (HILS) system. By reviewing the simulation and experimental results, it was found that the proposed scheme improves the output voltage and THD quality. [ABSTRACT FROM AUTHOR]

First-principle theory was used to design NaGdF4:Yb3+/Er3+ crystal, where the density of state, X-ray diffraction and optical coefficient had been studied through a generalised gradient approximation within density functional theory to predicate the effect of rare earth ion doping on the electronic and optical performance. Besides, NaGdF4:Yb3+/Er3+ nanoparticles were also obtained by liquid–solid–solution method and realized the enhancement of upconversion emission and the regulation of spectrum under co-excitation of the 980 nm and 1550 nm lasers. The results inspired us to establish upconversion logic gate system, where 'INHIBIT, OR, XOR, YES, AND' logic gate operations had been successfully developed by introducing external two excitation sources as input signals and monitoring the relative intensity signals of green and red emission bands and G/R ratio signal. [ABSTRACT FROM AUTHOR]

A critical area of research is studying the performance of semiconductor optical amplifiers (SOAs) at high temperatures. In this paper, the performance of all-optical exclusive-OR (XOR) logic gate is investigated at high operating temperatures (TOP) using different SOAs technologies such as conventional SOAs, carrier reservoir (CR)-SOAs, reflective SOAs (RSOAs), and photonic crystal (PC)-SOAs, for the first time to our knowledge. The time-dependent differential equations of SOAs, CR-SOA, RSOAs, and PC-SOAs at different operating data rates have been solved. The performance of the XOR logic gate is evaluated by calculating the quality factors and plotting the eye diagrams for each amplifier. Besides, the dependence of the key operating parameters on the TOP is examined and assessed for each scheme. The results showed that the RSOAs perform better at high temperatures than other proposed SOA technologies. [ABSTRACT FROM AUTHOR]

Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices. [ABSTRACT FROM AUTHOR]

A new type of cascading of Mach–Zehnder interferometer (MZI) structure is presented based on the electro-optic effect for simultaneous multiple operations of different logic families operation in this paper. Unit MZI as a switch to cascading-structure is presented, starting from the illustration of material characteristics to logic realization. It includes some exciting techniques to implement the simultaneous multiple optical logic operations through mathematical understanding along with the simulation of proposed devices using the MATLAB. After that, the realization of the proposed structure is done, on OptiBPM simulation software which provides comparative potential advantages of high-speed optical logic devices in the field of next-generation high-speed optical systems. These logic devices miniaturization may be useful for the development of a logical unit of the optical Arithmetic logic unit (ALU) of the future optical microprocessor system. [ABSTRACT FROM AUTHOR]

In this paper, we give a survey on the problem of how a Fredkin gate, a universal reversible logic gate, is realised in various reversible cellular automata (RCAs). Models of RCAs considered here are two kinds of square partitioned cellular automata (SPCAs), and four kinds of elementary triangular partitioned cellular automata (ETPCAs). These six RCAs are very simple, in particular, ETPCAs are extremely simple, yet they are computationally universal in the sense any reversible Turing machine, which is composed of Fredkin gates, can be embedded in them. There are three key points for implementing a Fredkin gate in an RCA: (1) realising a signal, (2) routeing a signal, and (3) interacting two signals. We shall see that depending on the properties of the RCAs, different techniques are used to realise the above three functions. Based on these techniques, complete configurations of Fredkin gates in the six RCAs are given. [ABSTRACT FROM AUTHOR]

Managing the speed and power trade-off is becoming increasingly challenging as the power supply voltage (Vdd) is scaled down in each era. Existing logic circuits that address the trade-off require more power. A new logic circuit made up of one PMOS and two NMOS is evaluated while coupled to a typical power delivery network (PDN). Simulated in a 0.09 µm CMOS, the present circuit not only reduces the supply current but also achieves a constant delay than the CSL, MCML and CS-CMOS while the Vdd switches from 0.7 to 1.1 V. Besides, the power consumption and delay sustain a shift of 0.14µW and 0.3ps, respectively, following a 1OC change in temperature. However, the power consumption reduces by 0.2µW for a Vdd drop of 1mV. But the effective supply voltage close to the circuit fluctuates as the PDN draws a sudden high current. This causes the delay to change and induces jitter in the output swing. The jitter introduced for a current ramp 0–40A in 10ns is 6.7ps. The usefulness of the present design is also observed by designing a latch, master-slave flip-flop (FF), frequency divider (FD) and ring oscillator (RO). Comparing the latch, FF, FD and RO built using the conventional, proposed designs and simulated in a 0.09-µm CMOS show the lowest power and delay. [ABSTRACT FROM AUTHOR]

The complexity of intra prediction in High-Efficiency Video Coding (HEVC) is increased significantly due to the incorporation of inherent features like variable-sized quadtree partitioned coding units and 35 angular modes that help in achieving better compression. This paper presents an efficient hardware architecture for the intra prediction that supports and comprises the above aspects and achieves a higher throughput to support high definition (HD) videos. A compact reusable reference buffer structure is implemented to limit the buffer size to 1 KB. A dedicated arithmetic unit to take advantage of the parallelism present in the prediction algorithm is incorporated, which allows the reuse of multipliers to reduce hardware resources. The loading of reference samples to buffers for prediction causes significant delays which are eliminated in our design. The entire architecture functions as a pipelined unit with no data dependency and generates eight samples/clock cycle in parallel. The design is implemented on a Field Programmable Gate Array (FPGA) platform operating at a frequency of 110 MHz. This makes it possible to support 4 K videos at 30 frames per second, with the resource cost of 16 K logic gates and 122 registers. [ABSTRACT FROM AUTHOR]

The following paper on "Antenna Pattern Synthesis Using the Quasi Newton Method, Firefly and Particle Swarm Optimization Techniques", presents a study of antenna array synthesis using the optimization methods on various parameters such as pattern shape, side lobe level reduction, placement of nulls, and beam width. The optimization performance is studied in simulation and inferences are made from the study. The last paper "Performance Analysis of Meningioma Brain Tumor Detection System Using Feature Learning Optimization and ANFIS Classification Method", is about the classification and segmentation of meningioma tumors. The following paper, titled "Miniaturised Triangular Microstrip Antenna with Metamaterial for Wireless Sensor Node Applications", presents the design of a compact triangular microstrip antenna with metamaterial for wireless sensor node applications. [Extracted from the article]

We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well. [ABSTRACT FROM AUTHOR]

In this paper, the design of a novel efficient QCA-based universal logic gate (ULG) is presented. Compact and efficient implementation layout with only one clock phase delay and also the implementation of the 13 standard functions without extra ULG or gate are the advantages of the proposed ULG. The results show that the proposed ULG is an efficient tool in designing any QCA circuit. Also, an accurate artificial neural network (ANN) model of the proposed ULG is presented. This model can be simply imported into any circuit simulators such as HSPICE, MATLAB Simulink and etc., for modeling and simulation of QCA circuits at the Gate level with high precision in a short time. [ABSTRACT FROM AUTHOR]

The DNA-based logic circuit has emerged as a potential member for the next-generation ultralow power application due to its rapid self-assemble technique, enormous parallelism, compatibility with various organic and inorganic molecules, and energy efficiency. Density functional theory coupled with non-equilibrium Green's function-based first principle approach is used in the investigation of quantum scattering transmission property of a single-strand DNA-based logic device using silicon carbide nanotube as electrodes at room temperature. The single-strand DNA nano-logic circuit exhibits high tunneling current in forward and reverse bias conditions for ± 1 V bias voltages. This proposed model can be exploited as bio-inspired logic circuit in future generation devices due to its satisfactory current–voltage response and the nature of resistance. [ABSTRACT FROM AUTHOR]

Riboswitch architectures that involve the binding of a single ligand to a single RNA aptamer domain result in ordinary dose-response curves that require approximately a 100-fold change in ligand concentration to cover nearly the full dynamic range for gene regulation. However, by using multiple riboswitches or aptamer domains in tandem, these ligand-sensing structures can produce additional, complex gene control outcomes. In the current study, we have computationally searched for tandem riboswitch architectures in bacteria to provide a more complete understanding of the diverse biological and biochemical functions of gene control elements that are made exclusively of RNA. Numerous different arrangements of tandem homologous riboswitch architectures are exploited by bacteria to create more 'digital' gene control devices, which operate over a narrower ligand concentration range. Also, two heterologous riboswitch aptamers are sometimes employed to create two-input Boolean logic gates with various types of genetic outputs. These findings illustrate the sophisticated genetic decisions that can be made by using molecular sensors and switches based only on RNA. [ABSTRACT FROM AUTHOR]

Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used. [ABSTRACT FROM AUTHOR]

We investigate the optical response of a hybrid cavity quantum-electrodynamics system consisting of a quantum dot embedded in an optomechanical photonic crystal cavity. The system is coupled to an auxiliary cavity via a waveguide that can support a single optical mode. We demonstrate the possibility of generating tunable optical bistability, double-bistabilty and tristability which can be utilized to design all-optical-switch and multi-valued logic circuits eventually forming a part of a large scale quantum communication platform. The proposed system has also found to exhibit the Mollow triplet and the Fano resonances modified by an optomechanical interaction. The optomechanically induced transparency (OMIT) is superimposed on the Fano resonance (OMIT-Fano resonance) having the transparency window occurring exactly at the point where the probe detuning becomes equal to the mechanical oscillator's resonant frequency. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the DC and RF behaviour of the novel Enhancement-Mode (E-Mode) Double-Gate High Electron Mobility Transistors (DGHEMTs) using Sentaurus-TCAD software. The scalability of the novel DGHEMT is also studied by analysing the short channel effects. The attractive features of the proposed DGHEMT are intrinsic In0.80Ga0.20As/InAs/In0.80Ga0.20As channel, dual silicon delta doping sheets and platinum (Pt) buried gate technology. The proposed DGHEMT with Lg = 20 nm exhibits a gm_max of 3970 mS/mm and IDS_max of 1650 mA/mm at VGS = 0.6 V and VDS = 0.8 V. The proposed DGHEMT exhibits a threshold voltage of 20 mV which indicates its E-Mode behaviour. The sub-threshold swing (SS) and DIBL values obtained for Lg = 20 nm DGHEMT at VDS = 0.5 V are 74 mV/dec and 78 mV/V respectively. The Lg = 20 nm proposed E-Mode DGHEMT also exhibit a fT and fmax of 826 and 1615 GHz respectively at VDS = 0.6 V. The computed logic gate delay for the Lg = 20 nm DGHEMT is 31.25 fS with an electron velocity under the gate of 6.4 × 107 cm/S. This excellent RF and DC behaviour of the proposed DGHEMT makes them an excellent choice for future sub-millimetre wave and THz frequency applications. [ABSTRACT FROM AUTHOR]

A novel colorimetric probe based on the bromopyrogallol red (BPR) for the sequential detection of Bi3+ and C2O42− was designed. The presence of Bi3+ led to a distinct naked-eye colour change in DMSO/H2O (1:3, v/v) media. The detection limit of BPR for Bi3+ was down to nanomolar concentration (1.17 nmol L−1). Also, the sensing ability of BPR for Bi3+ was successfully carried out in bismuth tablet and urine sample. Moreover, the resulting BPR-Bi3+ complex acted as an efficient colorimetric chemosensor for C2O42− via a colour change. Therefore, chemosensor BPR-Bi3+ can illustrate the ability to determine C2O42- up to 0.15 µmol L−1, selectively. Notably, the absorbance changes of BPR upon the addition of Bi3+ and C2O42− were utilised as AND and NAND logic gates operating at the molecular level with Bi3+and C2O42− as chemical inputs and the absorbance signal as the output. The chemical inputs of Bi3+ and C2O42- in a sequential system produce an output which mimics the operation of a security keypad lock. This study provides a practical application for the sensing of C2O42− ions in vegetable and urine samples by the construction of the supramolecular system. [ABSTRACT FROM AUTHOR]

In the current study, a novel and facile selective colorimetric approach was developed by Eriochrome Black T (EBT) for naked-eye detection and determination of nickel (Ni2+) and cyanide (CN−) ions in H2O/DMSO (9:1, v/v) media. The chemosensing behaviour of EBT has been indicated through UV-Vis absorbance spectra, visual colour changes, and FTIR spectra. First, EBT could selectively identify Ni2+ over other competitive cation in 90% aqueous media and then, the resulting EBT-Ni2+complex was successfully applied for selective colorimetric recognition of CN− based on azo-hydrazone tautomeric skeletons. The detection limit of EBT towards Ni2+ and CN− were calculated to be 0.06 µmol L−1 and 0.15 µmol L−1, respectively. These consequences represent an innovative type of nimble chemosensor for manifold target ions using simple colorimetric and sequential detection. When operated by chemical ions Ni2+ and CN− can act as an absorbance switch, distinguishing a multi-addressable system. In addition, INVERTER (INV) and INHIBIT (INH) logic gates at different wavelengths and a keypad lock were created by applying chemical ions Ni2+ and CN− as two inputs and an absorption mode at 541 nm as an output on the basis of suitable chemical stimuli. [ABSTRACT FROM AUTHOR]

The site-size hierarchy concept enables researchers to transform archaeological survey data into political classifications. Yet everything about the site-size rubric is worth re-thinking, from the reliability of surface-survey data to the recognition that sites of all sizes act autonomously within territorial configurations. New ways can visualize and analyze the process whereby complex societies (chiefdoms and states) emerge through the materialized energies of constituent parts (cities, towns, resource zones, fortifications, frontiers) that ebb and flow through connections of trade, warfare, alliances, and migration characterized by multiple and overlapping dynamisms among human and non-human elements, and in which historical trajectories form the basis of memory and action. Five alternative ways of mapping and analyzing relationships among sites are offered, derived from biological models of individual and collective interaction: reticulated hierarchies, logic gates, cellular automata, recurrent connectivity, and firefly synchronicity. [ABSTRACT FROM AUTHOR]