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This chapter presents the design of a test application that will utilize the circuit design methodologies described in Part II of this book. Sect. 14.2 discusses the criteria used to choose a test application and also an overviewof what basic building blocks are required for such an application. It also defines the design constraints that are to be taken into accountwhile designing a sub-threshold circuit. The architecture of the whole system and the details of the sub-blocks of the system are covered in Sect. 14.3. This chapter also outlines some special considerations and redundant features and failure-safe features that are built into the chip. The design of the chip is targeted for the TSMC [2] 0.25_m process, which is a triple well CMOS process.

In the first part of this book, we discussed the problems faced due to leakage and proposed techniques to minimize leakage. In the second part of this book, we propose techniques to exploit leakage instead of minimizing it. We do this through the use of sub-threshold circuit design.

Sub-threshold circuit design is an appealing means to dramatically reduce power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs.We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7×, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4×, compared to a traditional network of PLA design. Our approach is quite general and can be applied to traditional circuits as well.

Leakage power currently comprises a large fraction of the total power consumption of an IC. Techniques to minimize leakage have been researched widely. However, most approaches to reducing leakage have an associated performance penalty. In this chapter, we present an approach that minimizes leakage by simultaneously modifying the circuit while deriving the input vector that minimizes leakage. In our approach, we selectively modify a gate so that its output (in sleep mode) is in a state that helps minimize the leakage of other gates in its transitive fanout. Gate replacement is performed in a slack-aware manner, to minimize the resulting delay penalty. One of the major advantages of our technique is that we achieve a significant reduction in leakage without increasing the delay of the circuit.

The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. A heuristic approach (referred to as MLVC) is to determine the input vector that minimizes leakage for a combinational design. This approach utilizes approximate signal probabilities of internal nodes to aid in finding a minimal leakage vector. We utilize a probabilistic heuristic to select the next gate to be processed as well as to select the best state of the selected gate. A fast Boolean Satisfiability (SAT) solver is employed to ensure the consistency of the assignments that are made in this process. A variant of MLVC, referred to as MLVC-VAR, is also presented. MLVC-VAR includes the effect of random variations in leakage values due to process, voltage and temperature (PVT) variations. Including the effect of PVT variations for determining minimum leakage vector is crucial because leakage currents have an exponential dependence on power supply, threshold voltage and temperature. Experimental results indicate that our MLVC method has very low runtimes, with excellent accuracy compared to existing approaches. Further, the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector. MLVC-VAR reports, on average, about 9.69% improvement over MLVC with similar runtimes and 5.98% improvement over the random vector generation approach with significantly lower runtimes.

Chapter 2 described some existing leakage reduction techniques. Threemain classes of techniques were discussed – power gating, body biasing and input vector control. Each of these techniques have their pros and cons and there is no one “one-size-fitsall” technique that solves the leakage problem for all designs.

Operating circuits in the sub-threshold region or near the sub-threshold design can yield extremely low power circuits. However, for most applications that require ultra-low power, the lowest power solution is not necessarily the optimal solution from a minimum energy point of view. In this chapter, we describe a technique to find the energy optimum VDD value for a design, and show that for minimum energy consumption, the circuit may need to be operated at VDD values that are slightly higher than the NMOS threshold voltage value. We study this problem in the context of designing a circuit using a network of dynamic NOR-NOR PLAs.

With leakage power increasing as a fraction of the total power of a design, due to the current design trends, it is arguably important to find the leakage for all input vectors. This is useful when comparing candidate implementations of a design with the same minimum leakage values. An implementation that has a leakage histogram with larger number of input vectors contributing to lower leakage values would be preferred over other implementations. This would not only minimize the leakage during the regular operation of the circuit, but also ease the task of finding a vector that results in minimum leakage state.

While the first part of this book discussed leakage reduction techniques, the second part focused on leakage exploitation. In Chap. 9 we first presented data from some exploratory studies that revealed the opportunity that sub-threshold circuit design offers. The main advantages of sub-threshold circuits are as follows: ● Low power consumption and heat dissipation ● Smaller delays with increasing temperature ● High power-delay product (PDP)

In this chapter we cover all implementation aspects of the chip. We start with an overview of the design flow used (in Sect. 15.2. Next, in Sect. 15.3, we discuss how we translate the BFSK circuit (written in Verilog) to a netlist (of a network of PLAs). In Sect. 15.4, we discuss how we verify the dynamic compensation circuit through SPICE simulations. The design of the DAC and amplifier circuitry is covered in Sect. 15.5. Some special considerations that need to be taken care of for this chip, including some additions required for the sake of improved testability and improved yield are discussed in Sect. 15.6. In this section, we also discuss how we created separate voltage domains to enable a comparison of the sub-threshold implementation of the BFSK circuit with a regular super-threshold standard-cell-based version. The details of how we implemented the standard-cell-based version of the BFSK circuit are covered in Sect. 15.7. The design of the IO pads and the ESD structures used is covered in Sect. 15.8. In Sect. 15.9, we present how the entire chip was integrated and how we decided the pin-out for the IC. Layout details of the all the components of the IC are covered in Sect. 15.10. We explain how we verified the design before tape-out in Sect. 15.11.

In recent times, leakage power reduction has received much attention in academia as well as industry. Several means of reducing leakage power have been proposed. Some of these are mentioned here.

One of the most popular ways of reducing leakage is through the use high-VT power gating transistors (as in the MTCMOS technique [8,13] mentioned in Chap. 2). The HL approach is a variant of this technique that uses these power gating transistors selectively. In the HL approach we first create two low-leakage variants of each cell in a standard-cell library. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network. Similarly we minimize leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants of each standard cell are obtained. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design.

One of the main disadvantages of their sub-threshold circuits is their extreme sensitivity to variations in power supply, temperature and processing. In this chapter, we present a sub-threshold design methodology that automatically self-adjusts for inter and intra-die process, supply voltage and temperature (PVT) variations. This adjustment is achieved by performing bulk voltage adjustments in a closed-loop fashion. The design methodology uses medium-sized Programmable Logic Arrays (PLAs) as the circuit implementation structure. Details about the structure and operation of the PLAs are presented in Sect. 10.3. The design has a global beat clock to which the delay of a spatially localized cluster of PLAs is “phase locked”. The synchronization is performed in a closed-loop fashion, using a phase detector and a charge pump that drives the bulk nodes of the PLAs in the cluster. The details of this scheme are presented in Sect. 10.4. The experimental results presented in Sect. 10.5 demonstrate that our technique is able to dynamically phase lock the PLA delays to the beat clock, across a wide range of PVT variations, enabling the sub-threshold design methodology to be applicable in practice. We also present an analysis of the loop gain of this closed-loop adaptive body biasing technique in Sect. 10.6.

One of the methods to reduce leakage power is by increasing the threshold voltages (V T) of the device. This is done either statically, through use of multi-threshold devices or dynamically, through Reverse Body Biasing (RBB).

In recent times, dynamic supply voltage scaling (DVS) has been extensively employed to minimize the power and energy of VLSI systems. Also, sub-threshold circuits are becoming more popular. At the same time, the reliability of VLSI systems has become a major concern under Single Event Upsets (SEUs). SEUs are very problematic even for circuits operating at nominal voltages. With the increasing demand for low power reliable systems, it is therefore necessary to harden DVS and sub-threshold circuits efficiently. In this paper, we perform 3D simulations of radiation particle strikes in an inverter implemented using DVS and sub-threshold design. We analyze the sensitivity of the inverter to radiation particle strikes by varying the inverter size, the inverter load, the supply voltage (VDD) and the energy of the radiation particles. From these 3D simulations, we make several observations which are important to consider during radiation hardening of DVS and sub-threshold circuits. Based on these observations, we propose several guidelines for radiation hardening of DVS and sub-threshold circuit designs. These guidelines suggest that the traditional radiation hardening approaches need to be revisited for DVS and sub-threshold designs. We also propose a charge collection model for DVS circuits. Our model can accurately estimate (with an average error of 6.3%) the charge collected at the output of a gate for different supply voltages and different gate sizes for medium and high energy particle strikes. The parameters of our charge collection model can be included in SPICE model cards of transistors, to improve the accuracy of SPICE based radiation simulations for DVS circuits.

This chapter presents a model for the dynamic stability of an SRAM cell in the presence of a radiation particle strike. Such models are required since SRAM stability analysis is crucial from an economic viewpoint, given the extensive use of memory in modern processors and SoCs. Static noise margin (SNM)-based stability analysis often results in pessimistic designs because SNM cannot capture the transient behavior of noise events. Therefore, to improve the accuracy of SRAM noise analysis, dynamic stability should be considered. The dynamic model of SRAM stability proposed in this chapter utilizes the double exponential current pulse for modeling a radiation particle strike, and is able to predict (more accurately than the most accurate prior approach) whether a radiation particle strike will result in a state flip in a 6T-SRAM cell (for given values of Q, τα, and τβ). This model enables a designer to quickly (2,000 ×faster than SPICE) and accurately analyze SRAM stability during the design phase.

A process variation tolerant design approach for combinational circuits is presented in this chapter, which exploits the fact that random variations can cause a significant mismatch in two identical devices placed next to each other on the die. In this approach, a large gate is implemented using an appropriate number ( > 1) of smaller gates, whose inputs and outputs are connected to each other in parallel. This parallel connection of smaller gates to form a larger gate is referred to as a parallel gate. Since the L and V T variations are largely random and have independent variations in smaller gates, the variation tolerance of the parallel gate is improved. The parallel gates are implemented as single layout cells. By careful diffusion sharing in the layout of the parallel gates, it is possible to reduce the input and output capacitance of the gates, thereby improving the nominal circuit delay as well. An algorithm is also developed to selectively replace critical gates in a circuit by their parallel counterparts, to improve the variation tolerance of the circuit. Monte-Carlo simulations demonstrate that this process variation tolerant design approach achieves significant improvements in circuit level variation tolerance.

In this chapter, another radiation tolerant combinational circuit design approach is presented for combinational designs. This approach is called the split-output-based hardening approach. This hardening approach exploits the fact that if a gate is implemented using only PMOS (NMOS) transistors, then a radiation particle strike can result only in logic 0–1 (1–0) transients. Based on this observation, radiation hardened variants of regular static CMOS gates are derived. Split-output-based radiation hardened gates exhibit an extremely high degree of radiation tolerance, which is validated at the circuit level. Hence, this approach is suitable for hardening against medium and high energy radiation particles. Using these split-output gates, circuit level hardening is performed based on logical masking, to selectively harden those gates in a circuit, which contribute maximally to the soft error failure rate of the circuit. The gates whose outputs have a low probability of being logically masked are replaced by their radiation tolerant counterparts, such that the digital design achieves a soft error rate reduction of a desired amount (typically 90%). The split-output-based hardening approach is able to harden combinational circuits with a modest layout area and delay penalty.

In this chapter, an analytical model to efficiently estimate the shape of the voltage glitch that results from a radiation particle strike is presented. A model for the load current I out G (V in, V out) of the output terminal current of the gate G is used. The model presented in this chapter is applicable to any general combinational gate with different loading, and for arbitrary values of collected charge (Q). The effect of the ion track establishment constant (τβ) of the radiation particle induced current pulse is accounted for. The voltage glitch computed by this analytical model can be propagated to the primary outputs of a circuit using existing voltage glitch propagation tools. The properties of the voltage glitch (such as its magnitude, glitch shape, and width) at the primary outputs can be used to evaluate the SEE robustness of the circuit. On the basis of the result of this analysis, circuit hardening approaches can be implemented to achieve the level of radiation tolerance required. Experimental results demonstrate that the proposed analytical model is fast (at least 275 ×faster) and accurate (average root-mean-square-percentage error is 5%) compared with SPICE.

This chapter presents the sensitizable statistical timing analysis (StatSense) methodology, developed to remove the pessimism due to two sources of inaccuracy, which plague current statistical static timing analysis (SSTA) tools. Specifically, the StatSense approach implicitly eliminates false paths, and also uses different delay distributions for different input transitions for any gate. StatSense consists of two phases. In the first phase, a set of N logically sensitizable vector transitions which result in the largest delays for a circuit are obtained. In the second phase, these delay-critical sensitizable input vector transitions are propagated using a Monte-Carlo-based technique, to obtain the delay distribution at the outputs of the design. The specific input transitions at any gate are known after the first phase. The second phase performs Monte-Carlo-based SSTA, using the appropriate gate delay distribution corresponding to the particular input transition for each gate. The StatSense approach is able to significantly improve the accuracy of SSTA analysis. The circuit delay distribution obtained using StatSense closely matches with that obtained by SPICE-based Monte-Carlo simulations.

A novel process variation tolerant single-supply true voltage level shifter (SS-TVLS) design is presented in this chapter. It is referred to as “true” since it can handle both low-to-high, or high-to-low voltage level conversions. The SS-TVLS is the first published VLS design, which can handle both low-to-high and high-to-low voltage translation without a need for a control signal. The use of a single supply voltage reduces circuit complexity, by eliminating the need for routing both supply voltages. The proposed circuit was extensively simulated in a 90 nm technology using SPICE. Simulation results demonstrate that the level shifter is able to perform voltage level shifting with low leakage for both low-to-high, as well as high-to-low voltage level translation. The proposed SS-TVLS is also more tolerant to process and temperature variations, compared with a combination of an inverter along with the nontrue VLS.

In this chapter, an approach is developed to analyze the effect of radiation-induced transients in combinational circuits. Efficient and accurate models for radiation-induced transients are required to evaluate the radiation tolerance of a circuit. A radiation particle strikes at a node may result in a voltage glitch. The pulse width of this voltage glitch is a good measure of radiation robustness of a design. Thus, an analytical model to estimate the pulse width of the radiation-induced voltage glitch in combinational designs is presented in this chapter. In this approach, a piecewise linear transistor I DS model is used, and the effect of the ion track establishment constant (τβ) of the radiation-induced current pulse is considered. Both these factors improve the accuracy (in comparison with the previous approaches) of the analytical model for the pulse width computation. The model is applicable to any logic gate, with arbitrary gate size and loading, and with different amounts of charge collected due to the radiation strike. The model can be used to quickly (1,000 ×faster than SPICE simulations) determine the susceptible gates in a design (the gates where a radiation particle strike can result in a voltage glitch with a positive pulse width). The most susceptible gates can then be protected using circuit hardening approaches, based on the degree of hardening desired.

This chapter presents a radiation tolerant combinational circuit design approach, which is based on the clamping action of a diode. This diode clamping-based hardening approach is based on the use of shadow gates, whose task is to protect the primary gate in case it experiences a radiation strike. The gate to be protected is duplicated locally, and a pair of diode connected transistors (or diodes) is connected between the outputs of the original and the shadow gate. These diodes turn on when the voltage across the two gate outputs deviates (during a radiation strike). A methodology is also presented to protect specific gates of the circuit based on electrical masking, in a manner that guarantees radiation tolerance for the entire circuit while keeping the area and delay overhead low. An improved circuit level hardening algorithm is also proposed, to further reduce the delay and area overhead. Note that the diode clamping-based approach is suitable for hardening a circuit against low energy particle strikes.