Implementation of the Chip

In this chapter we cover all implementation aspects of the chip. We start with an overview of the design flow used (in Sect. 15.2. Next, in Sect. 15.3, we discuss how we translate the BFSK circuit (written in Verilog) to a netlist (of a network of PLAs). In Sect. 15.4, we discuss how we verify the dynamic compensation circuit through SPICE simulations. The design of the DAC and amplifier circuitry is covered in Sect. 15.5. Some special considerations that need to be taken care of for this chip, including some additions required for the sake of improved testability and improved yield are discussed in Sect. 15.6. In this section, we also discuss how we created separate voltage domains to enable a comparison of the sub-threshold implementation of the BFSK circuit with a regular super-threshold standard-cell-based version. The details of how we implemented the standard-cell-based version of the BFSK circuit are covered in Sect. 15.7. The design of the IO pads and the ESD structures used is covered in Sect. 15.8. In Sect. 15.9, we present how the entire chip was integrated and how we decided the pin-out for the IC. Layout details of the all the components of the IC are covered in Sect. 15.10. We explain how we verified the design before tape-out in Sect. 15.11.