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Silicon carbide particle reinforced aluminum matrix composites (SiCp/Al), combine the properties of aluminum matrix materials and reinforced silicon carbide (SiC) particles, finding widespread application in aerospace, optics, and electronics. The increased hardness and electrochemical inertness of SiC particles present significant challenges in their processing. This research investigates the impact of photocatalytic processes on machining accuracy in electrochemical processing (ECM). The dissolution characteristics of SiCp/Al during ECM and photocatalytic-assisted electrochemical machining (PAECM) were analyzed with varying electrolyte compositions, using polarization curves and oxidation–reduction potential (ORP). Validation of improved machining accuracy and surface quality in PAECM was achieved through no-feeding machining. According to theoretical principles and laboratory analyses of the workpiece surface, it was found that PAECM, through its photocatalytic reaction, generated more oxides, blocked stray currents and stray corrosion effectively, and attained accuracy in profile creation. Through a comparative analysis it revealed that PAECM exhibited smoother profiles and reduced Overcut Ratio (OCR) in hole and groove machining compared to ECM, particularly in groove machining. Adjusting machining gaps as well as reducing abrasive particle size in PAECM influenced groove depth and width, which achieved optimal morphology with a 0.4 mm gap and a 2–3 nm abrasive particle size, resulting in a 370 μm depth. [ABSTRACT FROM AUTHOR]

Nanofilm CdS@Cd/Si heterojunctions have been fabricated by a two-step method. The obvious rectification effect can be observed. However, the leakage current density is relatively large. According to the criterion for judging the conduction model, three conduction mechanisms can be observed, which are the thermally generated electrons model, the Ohmic model and the space-charge-limited-current model from low voltage to high voltage, respectively. The preparation process of nanofilm CdS@Cd/Si heterojunctions by this two-step method, which directly grows nanofilm CdS@Cd on the silicon substrate to construct heterojunctions, can reduce the introduction of excessive defects and facilitate the release of stress in the interface. [ABSTRACT FROM AUTHOR]

The ten-switch inverter is recently proposed in the literature to replace the neutral clamped point three-level inverter; it can produce a two/three-level output voltage using only ten switches. The conventional modulation strategies generate a large common mode voltage (CMV), which increases the leakage current. The use of the sinusoidal pulse width modulation (SPWM) produces a high CMV of Vdc/2. On the other hand, using conventional space vector modulation (SVM) methods can only reduce the CMV to Vdc/3. To achieve further reduction in the magnitude of the CMV, a new virtual SVM (VSVM) strategy is suggested. The space vector diagram is constructed with virtual vectors which can generate the lowest possible CMV (|VCM|= Vdc/6). In the proposed VSVM, the action times are calculated and the switching sequence is synthesized for each region. The VSVM is applied to a ten-switch inverter through a simulation, and it is validated experimentally. It is compared to some existing modulation techniques, such as the SPWM method, two SVM methods and the conventional VSVM. Simulation and experimental results showed that the proposed VSVM algorithm can effectively reduce CMV to Vdc/6. The use of virtual vectors does not affect the performance of the proposed algorithm in terms of the use of the DC bus voltage. In addition, it can effectively balance the neutral point voltage. However, the analysis of voltages and currents demonstrated that the use of virtual vectors increases the rate of harmonics compared to conventional SVM methods. [ABSTRACT FROM AUTHOR]

This study presents and examines the feasibility of a dual metal gate ferroelectric germanium heterojunction-based step channel double-gate tunnel field-effect transistor (SC-DMTFET) to eliminate issues pertaining to drive current, subthreshold swing, and leakage current, concurrently decreasing ambipolar behavior resulting from structural similarities between the source and drain ends. Mitigating the consequences of ambipolar effects is the purpose of the study. The performance of the proposed structure was assessed and compared to that of a single metal gate, both with and without a step channel, by utilizing various TCAD simulation parameters. An analysis of the energy diagram, carrier concentration, electric field, drain characteristics, surface potential, and analog/radio frequency (RF) parameters was conducted to evaluate the electrostatic behavior of all the structures. The proposed structure yields minimum OFF current of 2.10 × 10−17 A/μm and maximum ON current of 2.33 × 10−3 A/μm. Also, the SC-DMTFET exhibits the highest current ratio of ≃1014 and the minimum subthreshold slope of 26.17 mV/decade in all designed structures. [ABSTRACT FROM AUTHOR]

ZnO varistor samples generally have poor preparation repeatability. In this work, ZnO varistor samples A and B with the same preparation technique showed significant differences in properties, and the reasons were explored in detail. Nonlinear coefficient (α) values of 42.59 and 72.68, and leakage current density of 0.013 mA/cm2 and 0.002 mA/cm2 were found for samples A and B, respectively, which are markedly different between the samples. However, samples A and B showed the same phases. In addition, samples A and B exhibited mean grain size (d) of 2.21 μm and 2.47 μm, double Schottky barrier height (φB) of 0.45 eV and 0.48 eV, and grain boundary resistivity (ρgb) of 5.32 × 106 Ω m and 5.40 × 106 Ω m, respectively, which were all similar between the two samples. According to the low-temperature dielectric spectral analyses, the values of k1 of samples A and B, reflecting the concentration of interstitial zinc, were 14.06 and 11.09, and the values of k2 reflecting the concentration of oxygen vacancy were 7.48 and 3.35, respectively. Therefore, the obvious difference in the electrical properties between samples A and B may be caused mainly by the obvious difference in the concentration of oxygen vacancy. Thus, this work provides evidence of the effects of oxygen vacancy on the electrical properties of ZnO varistors. [ABSTRACT FROM AUTHOR]

In this study, the effects of Al2O3 and Y2O3 passivation layers on Ge substrates are investigated to enhance the thermal stability of Ge-based devices. Using X-ray photoelectron spectroscopy, we analyze the growth characteristics and chemical composition of Al2O3, Y2O3, and ZrO2 on Ge. The changes in the crystallinity of ZrO2 on different substrates of Ge, Al2O3/Ge, and Y2O3/Ge configurations are observed via X-ray diffraction. Material properties, including capacitance, flat band voltage shift (ΔVFB), oxide charge trap (Not), interface defect density (Dit), and leakage current, are analyzed using the metal–oxide–semiconductor capacitor, with a particular focus on their electrical characteristics. Additionally, we investigate whether the passivation mechanisms of each material are more suitable for enhancing thermal stability. Overall, this study provides insight into the role of passivation layers in improving the interface and thermal stability of Ge-based devices, offering valuable contributions to the advancement of semiconductor technology. [ABSTRACT FROM AUTHOR]

The long-term operation performance of HVDC transmission systems is significantly influenced by the reliability of thyristors. However, the current reliability research of thyristors is mainly based on the leakage current and there is no comprehensive degradation characteristics of thyristors. In this article, the degradation characteristics of thyristors under voltage and temperature accelerated ageing tests are obtained, including the reverse recovery characteristic, on-state characteristic, blocking characteristic and gate characteristic. The reverse recovery characteristic obviously degrades under the voltage accelerated ageing tests. The reverse recovery charge and reverse recovery time decrease by over 10% after the tests. Seven thyristors operating for a certain number of years from two HVDC stations are tested, and the results verify the thyristor degradation characteristics obtained from the ageing tests. Moreover, the mechanisms of the leakage current and reverse recovery characteristic are analyzed in detail. [ABSTRACT FROM AUTHOR]

It is necessary to achieve current matching for GaN-based CMOS-like inverters. However, due to the low hole mobility of GaN p-FET devices, the weak output capacity of GaN p-FET devices makes it difficult to obtain current matching with n-FET devices in the off-state, which hinders the development of GaN-based CMOS-like inverters. In this study, a GaN-based CMOS-like device with an AlGaN back barrier layer is designed and its off-state leakage current is compared with that without an AlGaN back-barrier layer. The results show that the 2DEG confinement in the GaN-based n-FET device with an AlGaN back barrier layer can be enhanced and the leakage current is reduced from 10–3 A to 10–6 A in the off-state. This is accomplished without influencing the current of the GaN-based p-FET device in the off-state, resulting in a good current consistency between the n-FET device and the p-FET device in the off-state. The static power consumption is 4.5 µW for GaN-based CMOS-like inverters with an AlGaN back barrier structure when it is operated at Vdd = 5 V. The rise time (tr) and fall time (tf) of the GaN-based CMOS-like inverters are 4 μs and 0.12 μs, respectively. The low noise margin (NML) is 1.90 V and the high noise margin (NMH) is 2.55 V. This work lays a foundation for the development of the future of GaN-based integrated ICs. [ABSTRACT FROM AUTHOR]

An analytical study of the effect of gadolinium-doped ceria (GDC) electrolyte parameters on the output voltage, output power, open circuit no-load voltage, and leakage current is carried out for solid oxide fuel cell (SOFC). Conductivity due to both ions and electrons is considered for GDC electrolytes. The model incorporates various polarization losses such as activation overpotential, concentration overpotential, and ohmic potential losses in order to study the effect of electrolyte parameters on output voltage. The output voltage and, hence, the power density obtained from the model closely match the experimental reports, thus validating the model. Subsequently, the open circuit no-load voltage model and no-load leakage current are used to study the effect of electrolyte thickness and electronic conductivity on it during no-load conditions. During loaded condition, the model relating the electronic current with the ionic current is employed to analyze the effect of various SOFC parameters governing the electronic current density. This study will be instrumental in designing SOFC with low leakage current density and high output power in order to enhance the performance of SOFC. [ABSTRACT FROM AUTHOR]

We developed high-performance flexible oxide thin-film transistors (TFTs) using SnO2 semiconductor and high-k ZrO2 dielectric, both formed through combustion-assisted sol-gel processes. This method involves the exothermic reaction of fuels and oxidizers to produce high-quality oxide films without extensive external heating. The combustion ZrO2 films were revealed to have an amorphous structure with a higher proportion of oxygen corresponding to the oxide network, which contributes to the low leakage current and frequency-independent dielectric properties. The ZrO2/SnO2 TFTs fabricated on flexible substrates using combustion synthesis exhibited excellent electrical characteristics, including a field-effect mobility of 26.16 cm2/Vs, a subthreshold swing of 0.125 V/dec, and an on/off current ratio of 1.13 × 106 at a low operating voltage of 3 V. Furthermore, we demonstrated flexible ZrO2/SnO2 TFTs with robust mechanical stability, capable of withstanding 5000 cycles of bending tests at a bending radius of 2.5 mm, achieved by scaling down the device dimensions. [ABSTRACT FROM AUTHOR]

BiFe0.91Zr0.09O3 (9BFZrO)/LaNiO3 (LNO)/MgO and 9BFZrO/LNO/Si multilayers were prepared by the sol–gel method using MgO and Si single crystals as substrates, and LNO films with a thickness of approximately 50 nm were deposited by magnetron sputtering to form bottom electrodes and transition layers. The effects of different substrates on the crystal structure, phase composition, oxygen vacancy content, ferroelectric properties, dielectric properties, leakage mechanism, and ageing properties of the 9BFZrO films were systematically analysed. X-ray diffraction showed that the prepared 9BFZrO thin films had a structure composed of both rhombic R3c and orthogonal Pnma phases, and the films prepared on the MgO substrate contained a significant amount of the R3c phase. SEM analysis showed that the thin film prepared on the MgO substrate had a relatively large grain size. X-ray photoelectron spectroscopy showed that the Fe2+ content and oxygen vacancy defect concentration of the MgO substrate samples were relatively low. The thin film prepared on the MgO substrate has a high residual polarization strength (2Pr = 60.28 μC/cm2) and a low leakage current density (4.71 × 10−6 A/cm2). After 90 days of room-temperature ageing, the residual polarization strength (2Pr) of the film on the MgO substrate decreased by 16.8%, with a lower ageing degree and better stability. [ABSTRACT FROM AUTHOR]

Quasi-two-dimensional perovskite light-emitting diodes (quasi-2D PeLEDs) are emerging as high-potential candidates for new generation of wide-color gamut displays due to their simple, low-cost solution process, and high color purity. However, the luminescence performance of quasi-2D perovskite films is severely limited by dispersed phase distribution and excessive defect density, which are caused by excessive diffusion of nucleation sites during the perovskite growth stage. Here, the benzylphosphonic acid (BPA) molecule, owing to its strong P-O-Pb bond energy sites and strong electronegativity to PEA+, can aggregate lead-halide octahedron to grow high-dimensional phases, avoiding scattered low-dimensional phases (n = 1). The continuous gradient phase distribution will be beneficial to smooth carrier injection and effectively suppress the leakage current in PeLEDs. Meanwhile, the introduction of phosphonic acid groups will fill the vacancies of Pb ions and reduce non-radiative recombination. As a result, the maximum external quantum efficiency (EQE) of PeLEDs can be increased from 8% to 20.6% with a 514 nm light emission and a 21 nm full-width half maximum, and the device lifetime (T50) is nearly 6-fold of the pristine sample. In addition, this strategy is also suitable for other wavelength. For example, in blue light, performance improvement is also realized that the maximum EQE of 8% and the luminance increased from 1045 to 5264 cd/m2. These results provide a feasible strategy to regulate the phase distribution and passivate the defects of quasi-2D perovskites. [ABSTRACT FROM AUTHOR]

The observation of the gate-controlled supercurrent (GCS) effect in superconducting nanostructures increased the hopes for realizing a superconducting equivalent of semiconductor field-effect transistors. However, recent works attribute this effect to various leakage-based scenarios, giving rise to a debate on its origin. A proper understanding of the microscopic process underlying the GCS effect and the relevant time scales would be beneficial to evaluate the possible applications. In this work, we observed gate-induced two-level fluctuations between the superconducting state and normal state in Al/InAs nanowires (NWs). Noise correlation measurements show a strong correlation with leakage current fluctuations. The time-domain measurements show that these fluctuations have Poissonian statistics. Our detailed analysis of the leakage current measurements reveals that it is consistent with the stress-induced leakage current (SILC), in which inelastic tunneling with phonon generation is the predominant transport mechanism. Our findings shed light on the microscopic origin of the GCS effect and give deeper insight into the switching dynamics of the superconducting NW under the influence of the strong gate voltage. It was recently shown that a voltage could be used to control a supercurrent in superconducting nanostructures, much like a transistor, however, the exact origin of this effect has been debated. Here Elalaily et al. show via noise measurements that the suppression of the supercurrent in the superconducting device arises due to excitation emission by inelastic tunneling of the electrons through the trap states created by stressing the oxide layer between the gate and the NW under a high electric field. [ABSTRACT FROM AUTHOR]

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation. [ABSTRACT FROM AUTHOR]

This paper proposes a single-stage, 5-L common-ground-based inverter for grid-connected photovoltaic (PV) applications. The suggested design is able to enhance the PV input voltage by charging and discharging the capacitors in sequence. In order to achieve this, a peak current controller-based method that controls both the active and reactive powers that are injected into the grid is employed to create the pulses that are used to activate the power switches. The injected current dynamics are controlled using a phase-locked loop system. The performance of the suggested topology is evaluated using the MATLAB/Simulink software. The simulation results indicate that the proposed topology outperforms the other topologies in terms of component count, total standing voltage, and cost factor as well as the removal of leakage current. In addition, the performance of a prototype designed out of scaled-down hardware is also tested in the testing facility. This suggests that the utilization of proposed MLI and its corresponding control techniques exhibit efficacy in attaining the intended performance goals. [ABSTRACT FROM AUTHOR]

In current years, the growth of high-k dielectric thin films with reduced charge density and leakage current has drawn tremendous attention for microelectronic devices. Ta2O5 thin film is deposited on p-type silicon substrate using radio frequency sputtering deposition technique for high-k dielectric applications. The as-deposited films undergo post-deposition annealing treatment at temperatures ranging from 600 °C to 900 °C for 1 h in air ambient. X-ray diffraction analysis revealed the formation of a polycrystalline orthorhombic β – Ta2O5 structure in the annealed films. The RMS roughness of the film is found to be increased from 2.3 nm to 3.7 nm with the increase in annealing temperature to 900 °C. Metal–oxide–semiconductor (Al/Ta2O5/p-Si) structures are fabricated using thermal evaporation for electrical characterizations. The capacitance-voltage (at 1 MHz) of this structure is measured for the sweep voltage from − 4 V to + 4 V. The oxide charge density and interface charge density of the film have been calculated from the C-V curve and found to decrease with the increase in annealing temperature. The highest dielectric constant value of 24.5 at 1 MHz is found for film annealed at 800 °C. The leakage current is measured from the current-voltage measurement and found to be minimum for the film annealed at 800 °C. [ABSTRACT FROM AUTHOR]

Using gallium nitride (GaN) transistors in motor drive systems presents challenges because of their high dv/dt characteristics. Compared with silicon (Si) transistors, GaN transistors cause a higher leakage current in the bearing. This phenomenon results in a bearing corrosion problem in the motor, consequently shortening its lifespan. In response to these challenges, an output filter placed between an inverter and the motor has been studied recently. This paper compares the leakage current in a permanent magnet synchronous motor (PMSM) drive system driven by a GaN inverter without and with a sine wave filter. By modeling the impedance of the leakage current path, this paper confirms the possibility of reducing leakage current with the application of the sine wave filter. Experimental results show that using the sine wave filter reduces the leakage current by 32.24% at full load. [ABSTRACT FROM AUTHOR]

This study investigates the synthesis and electrical property tailoring of BaZrxTi1-xO3 (BZT) ferroelectric films through Zr content variation, offering new insights into non-ferroelectric resistive switching (RS) mechanisms. Using a sol–gel spin-coating technique, BZT films with varying Zr compositions (x = 0.2, 0.4, 0.6, and 0.8) were deposited on (001)-oriented Si substrates. Our investigation reveals the intricate influence of Zr doping on crystalline structure, morphology, dielectric response, energy storage capability, ferroelectric polarization, leakage current, conductive mechanism, and RS behaviors. Notably, lower Zr4+ substitution for Ti4+ enhances grain growth and morphology, resulting in superior dielectric properties. Films with Zr doping below 40% demonstrate exceptional crystalline quality, higher dielectric constant, increased polarization withstand voltage, and reduced leakage currents. Remarkably, above 40% Zr concentrations, despite declines in these properties, a robust RS phenomenon emerges and strengthens with increased Zr doping. This RS behavior, attributed to the formation and rupture of conductive filaments rather than ferroelectric polarization, opens new pathways for developing advanced non-volatile memory devices. Our findings offer a breakthrough in understanding and engineering BZT films, providing a strategic foundation for future electronic and memory applications. [ABSTRACT FROM AUTHOR]

The corrosion behavior of Al/Ni-doped Cu alloys in seawater environments was investigated. Results indicated that increasing immersion temperature significantly worsened the corrosion resistance of Cu alloys in soil simulation and 3.5 wt.% NaCl solution. With the increase of stray current densities, the proportion of CuCl was significantly increased. The presence of stray current seriously destroyed the oxide film on the sample surface, thereby resulting in the deterioration of corrosion resistance. [ABSTRACT FROM AUTHOR]

Electric heaters based on functional materials and innovative designs have been developed for various applications. In this paper, we propose a soft dielectric heater (SDH) using polyvinyl chloride-gel (PVC-gel) as the dielectric heater and hydrogel as stretchable electrodes. Under an AC voltage, the leakage current in the PVC-gel leads to continuous injection and discharge of charges, causing the polarized plasticizers and flexible PVC chains to vibrate and collide, thereby generating heat through dielectric heating. Furthermore, the SDH generates a uniform temperature distribution even under strains up to 400%. Besides, high transmittance over 86% across the visible range renders it suitable for wearable or skin-mountable heaters from an esthetic viewpoint. Its capacitor-like structure achieves a scalable design, enabling extension from a singular cell to a row/column addressable and pixelated array of heaters. The 5 × 5 SDH array can deliver varied thermal information and sensations while maintaining performance even when stretched. [ABSTRACT FROM AUTHOR]

With the rapid development of urban rail transit, the issue of stray current due to incomplete insulation between the rail and the earth is attracting increasing attention. Stray current seriously affects the safe operation of urban rail transit, pipelines and power grids, and pose challenges to the development of urban energy security. However, there are significant differences among the various methods for the analysis and verification of stray currents, and existing research works thus lack a mature theoretical framework. To address this, this paper presents an in-depth review on the study of stray current including the mechanism, technical standards, modelling, simulation and mitigation technologies. Firstly, the principle and standards of stray current are introduced from multiple perspectives (i.e. metro side, pipeline side and grid side). Then, the typical modelling and simulation of stray current are summarized and compared in detail. The representative stray current mitigation measures, together with the stray current hardware simulation technologies, are also discussed. In conclusion, this paper provides a comprehensive overview of key technologies involved in the modelling and simulation of stray current, and highlights the valuable research direction in stray current mitigation. [ABSTRACT FROM AUTHOR]

In dual traction power supply systems, the overhead catenary system operates in different power supply modes. It passes across the AC section, DC section, and a neutral part, which influences the features and properties of the feedback current and aggregates its effects on stray current and rail potential. This research paper presents an integrated model of an AC and DC traction power system (TPS), along with a unified chain equivalent circuit model, the ground wire through the AC section, and the insulation joints fixed in the AC–DC neutral section under different operating positions. To make a unified impedance and admittance matrix for traction network, a virtual conductor wire has been added in the DC section to make the balance order of the TPS. The influence of reflex system configuration on rail potential, stray current, and distribution of rail potential at AC and DC stations has also been calculated. The simulation results demonstrate that establishing the insulation joints in the AC–DC section and using ground wires in the AC part can significantly decrease the stray current and rail potential. [ABSTRACT FROM AUTHOR]

Running rails are the return conductors of the traction current in DC subway systems, which should be insulated from the earth. Due to the large length of the line, as well as the humidity and metal dust in the tunnel, grounding fault of the running rails usually occurs, which will increase stray current (SC) leakage and endanger power supply safety. In this paper, a method of grounding fault diagnosis of running rails based on a multi-scale one-dimensional convolutional neural network (MS-1DCNN) is proposed. Firstly, a platform for the dynamic distribution of SC and rail potential (RP) with grounding faults existing in the running rails is established, which generates the dynamic RP data with various grounding faults. Secondly, a grounding fault diagnostic method of running rails based on MS-1DCNN is proposed, so as to realize the effective identification of ground fault types in subway systems. Thirdly, with the proposed diagnostic method, the datasets under two operating conditions of a single train and two trains are tested; a comparison test between MS-1DCNN and the 1D convolutional neural network (1DCNN) is carried out, and the effectiveness of the proposed method is verified. Results demonstrate that the proposed model can significantly improve the ground fault diagnostic accuracy of running rails. The dynamic RP simulation platform for trains established in this paper lays a theoretical foundation for the grounding fault research of running rail. Moreover, the deep learning method is proposed for the first time to diagnose the grounding fault of running rail, and the high diagnostic accuracy is obtained, which is of great significance for the safe and stable operation of the subway line. [ABSTRACT FROM AUTHOR]

In this study, Ga2O3 blocking layers (BLs) are used to improve the properties of dye-sensitized solar cells (DSSCs) by sputtering. The wide energy bandgap of Ga2O3 BLs not only can passivate the surface defects of TiO2 working electrodes but also can prevent the reverse leakage current from narrow energy bandgap of TiO2 working electrode. Compared with conventional narrow energy bandgap BLs, wide energy bandgap BLs are more effective in enhancing the power generation efficiency of DSSCs. After Ga2O3 BL deposited on TiO2 working electrode, the proportions of Ti3+ and Ti2+ can be reduced and the proportion of stable valence Ti4+ can be increased considerably. Moreover, the efficiency of DSSC with Ga2O3 BL increased from 4.06% to 5.72%. According to the results of electrochemical impedance spectroscopy analysis, the Ga2O3 BL increased the DSSC carrier lifetime from 0.17 to 0.35 ms and charge collection efficiency from 55.28% to 61.77%. Accordingly, the results of this study indicate that wide energy bandgap Ga2O3 BLs effectively prevent the formation of reverse leakage current, passivate working electrode defects in DSSCs, and are suitable for improving the performance of optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this study, arrays of μLEDs in four different sizes (5 × 5 μm2, 10 × 10 μm2, 25 × 25 μm2, 50 × 50 μm2) were fabricated using a flip-chip bonding process. Two passivation processes were investigated with one involving a single layer of SiO2 deposited using plasma-enhanced chemical vapor deposition (PECVD) and the other incorporating Al2O3 deposited by atomic layer deposition (ALD) beneath the SiO2 layer. Owing to superior coverage and protection, the double-layers passivation process resulted in a three-order lower leakage current of μLEDs in the 5 μm chip-sized μLED arrays. Furthermore, higher light output power of μLEDs was observed in each chip-sized μLED array with double layers passivation. Particularly, the highest EQE value 21.9% of μLEDs array with 5 μm × 5 μm chip size was achieved with the double-layers passivation. The EQE value of μLEDs array was improved by 4.4 times by introducing the double-layers passivation as compared with that of μLEDs array with single layer passivation. Finally, more uniform light emission patterns were observed in the μLEDs with 5 μm × 5 μm chip size fabricated by double-layer passivation process using ImageJ software. [ABSTRACT FROM AUTHOR]

Potassium sodium niobate (KNN) has attracted much interest as a promising lead-free ferroelectric candidate with its excellent physical properties for potential applications to novel nano-devices such as non-volatile ferroelectric memory. However, the use of KNN films in actual devices has been limited due to concerns in operational reliability (i.e., a polarization fatigue property). In this work, we demonstrate the enhancement of a polarization fatigue behavior in KNN thin films by doping of Mn ions. Ferroelectric fatigue is significantly suppressed in 0.4 mol% Mn-doped KNN films compared with pure KNN films. The amounts of mobile charged defects (e.g., oxygen vacancies and hole carriers produced with cation vacancies) are reduced in the presence of multivalent Mn dopants resulting in a decrease of leakage current density. The reduction of charged defect density can weaken the domain wall pinning effect enabling the polarization fatigue to be suppressed in KNN films. Our work is of practical interest for realizing lead-free ferroelectric memory devices with high performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel biosensor, the graded channel gate-all-around (GC-GAA) silicon nanowire-FET biosensor, which utilizes dielectric modulation through a cavity carved from the drain side for label-free biomolecule detection. The biomolecules that become fixed in the cavity region alter the device's electrical properties, such as impedance, resistance, capacitance, and charge field effect, resulting in changes in the biosensing device's threshold voltage, drain current, and sub-threshold slope. The cavity length varies between 10 and 14 nm, and different dielectric constants are used. The study investigates the effect of various biomolecules on the device's performance, including drain current (for dielectric constant = 1 and3.57), sub-threshold slope, threshold voltage, switching ratio, energy band, transconductance, and electric field. The obtained drain currents for device-1 are 2.96 µA and 2.75 µA with threshold voltage of 0.78 V and 0.76 V for S_D/D_S graded channel respectively for copper as gate metal. Similarly the drain currents for device-2 are 0.97 µA and 1.13 µA with threshold voltage of 0.73 V and 0.68 V for S_D/D_S graded channel respectively. However, for device-3 the drain currents are 0.91 µA and 1.08 µA with threshold voltage of 0.73 V and 0.67 V. The results indicate that higher dielectric constants result in higher drain current levels and increased device sensitivity. The GC-GAA-NWFET biosensor demonstrated high sensitivity (~ 138 mV) and low leakage current, making it a promising candidate for biosensing applications. [ABSTRACT FROM AUTHOR]

This paper investigates the ferroelectric and structural properties of BiFeO3 thin films with four different RE2O3 (Nd2O3, Eu2O3, Ho2O3, and Er2O3) buffer layers fabricated on a SrRuO3/n+-Si substrate through spin-coating. To analyze the BiFeO3 films with RE2O3 buffer layers, various techniques, such as X-ray diffraction, secondary ion mass spectrometry, atomic force microscope, and X-ray photoelectron spectroscopy were employed to investigate the crystalline structures, depth profiles, surface topographies, and chemical compositions. It was found that the BiFeO3 film with RE2O3 buffer layers exhibited improved electrical properties such as leakage current, remnant polarization, and coercive field compared to the control BiFeO3 film without a buffer layer. Moreover, the Eu2O3 buffer layer exhibited the lowest leakage current of 2.05 × 10–6 A/cm2, the highest remnant polarization of 43.76 μC/cm2, and the smallest coercive field of 188 kV/cm among all the RE2O3 buffer layers. The outcome is likely to have been caused by the introduction of Eu3+ ion to the BiFeO3 film, which resulted in a reduction in surface roughness, a significant preferred orientation of (110), and an increased concentration of Fe3+ ion. Consequently, this inhibited the fluctuation of Fe3+ to Fe2+ ions and reduced the occurrence of oxygen vacancies. [ABSTRACT FROM AUTHOR]

The hazard of stray current attracts more and more attention due to the potential infrastructure failure caused by the electrochemical corrosion. In view of the poor insulation performance and lack of stray current collection system in the metro depot, stray current leakage becomes particularly evident in this area. In order to evaluate the corrosion risk of buried metal pipeline surrounding metro depot, an assessment model for interference scope induced by stray current is proposed in this paper. The distribution of stray current is calculated based on the resistive network by considering different boundary conditions in different areas of metro depot, and the interference scope is assessed by surface potential gradient for corrosion risk of corroded pipeline. Moreover, the characteristics of surface potential gradient distribution in different areas of metro depot and the influence of electrical parameters are analyzed. Finally, the proposed model is verified through simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper investigates the ferroelectric and structural properties of BiFeO3 thin films with four different RE2O3 (Nd2O3, Eu2O3, Ho2O3, and Er2O3) buffer layers fabricated on a SrRuO3/n+-Si substrate through spin-coating. To analyze the BiFeO3 films with RE2O3 buffer layers, various techniques, such as X-ray diffraction, secondary ion mass spectrometry, atomic force microscope, and X-ray photoelectron spectroscopy were employed to investigate the crystalline structures, depth profiles, surface topographies, and chemical compositions. It was found that the BiFeO3 film with RE2O3 buffer layers exhibited improved electrical properties such as leakage current, remnant polarization, and coercive field compared to the control BiFeO3 film without a buffer layer. Moreover, the Eu2O3 buffer layer exhibited the lowest leakage current of 2.05 × 10–6 A/cm2, the highest remnant polarization of 43.76 μC/cm2, and the smallest coercive field of 188 kV/cm among all the RE2O3 buffer layers. The outcome is likely to have been caused by the introduction of Eu3+ ion to the BiFeO3 film, which resulted in a reduction in surface roughness, a significant preferred orientation of (110), and an increased concentration of Fe3+ ion. Consequently, this inhibited the fluctuation of Fe3+ to Fe2+ ions and reduced the occurrence of oxygen vacancies. [ABSTRACT FROM AUTHOR]

Aiming at the problems of low target detection accuracy and high leakage rate of the current traditional weld surface defect detection methods and existing detection models, an improved YOLOv7 pipeline weld surface defect detection model is proposed to improve detection results. In the improved model, a Le-HorBlock module is designed, and it is introduced into the back of fourth CBS module of the backbone network, which preserves the characteristics of high-order information by realizing second-order spatial interaction, thus enhancing the ability of the network to extract features in weld defect images. The coordinate attention (CoordAtt) block is introduced to enhance the representation ability of target features, suppress interference. The CIoU loss function in YOLOv7 network model is replaced by the SIoU, so as to optimize the loss function, reduce the freedom of the loss function, and accelerate convergence. And a new large-scale pipeline weld surface defect dataset containing 2000 images of pipeline welds with weld defects is used in the proposed model. In the experimental comparison, the improved YOLOv7 network model has greatly improved the missed detection rate compared with the original network. The experimental results show that the improved YOLOv7 network model mAP@80.5 can reach 78.6%, which is 15.9% higher than the original model, and the detection effect is better than the original network and other classical target detection networks. [ABSTRACT FROM AUTHOR]

Metal oxide arrester (MOA) is an electric power equipment used to limit overvoltage and cooperate insulation between generator substation and direct current converter station. In the actual operation of MOA, due to the abnormal leakage current will produce various faults, the significant increasing of its resistive component will cause thermal effect, and even explosion, so as to lose the protection for the MOA. Particularly, in the transition from preventive maintenance to state maintenance, the importance of its safe operation or fault diagnosis is undoubted. Since the 1990s, fault diagnosis of MOA in operation has been very popular, and it is still popular today. After decades of unremitting efforts, we have accumulated rich experience in fault diagnosis of MOA, and also explored some new fault diagnosis methods and means. With the rise of wireless network technology, its network construction, maintenance, and other aspects have incomparable advantages of wired. Therefore, adopting wireless online monitoring to track MOA status can greatly improve the flexibility, real-time, and accuracy of fault diagnosis, and reduce the error and cost of wired data transmission. In this study, the monitoring module can realize the real-time transmission of MOA operation characteristics to the control terminal through wireless networks, judge the running status and insulation performance of the MOA by the change of the basic component of the resistance current, and then diagnose the fault of the MOA by the proposed weighted k-nearest neighbors algorithm. The simulation results show that the proposed method has very high precision and accuracy in fault diagnosis of MOA, as well as high recall and F1. [ABSTRACT FROM AUTHOR]

III-nitride high-electron-mobility transistors (HEMTs) are the optimal choices for high-RF and power applications due to their exceptional performance characteristics. Nevertheless, HEMTs face formidable challenges related to large gate and buffer leakage currents, which inevitably impose significant limitations on device performance and reliability. In response to these challenges, this work studies the design consideration of a T-shaped gate InAlN/AlN with polarized doped buffer HEMT. The simulation results show that the parasitic capacitances are deeply affected by the geometry of the T-gate. The less influence of gate-to-source capacitance (Cgs) by the drain voltage possesses constant depletion charges at the source side, leading to a persistent value of Cgs with drain bias. Moreover, a polarization-doped buffer layer has been incorporated, effectively enhancing the confinement of the two-dimensional electron gas by causing an upward convex bend in the conduction band. This strategic design element significantly contributes to the reduction in leakage current (10−8), positive shift of Vth (0.9 V), and improves the switching ratio (108). The effect of gate head length (Hlength), gate stem height (Sheight), and gate foot length (Flength) on various RF parameters has been investigated. The simulated results confirm that the proper choice of Hlength (280 nm), Sheight (100 nm), and Flength (10 nm) significantly reduced the parasitic capacitance (Cgs = 350 fF/mm and Cgd = 140 fF/mm) and enhanced the Fmax (840 GHz), GBP (636 GHz), Ft (583 GHz) and also improved the power gains. The extracted results of the proposed design exhibit its efficacy for high-performance RF/microwave applications. [ABSTRACT FROM AUTHOR]

Water conservation has become a global problem as the population increases. In many densely populated cities in China, leaks from century-old pipe works have been widespread. However, entirely eradicating the issues involves replacing all water networks, which is costly and time-consuming. This paper proposed an AI-enabled water-saving control system with three control modes: time division control, flow regulation, and critical point control according to actual flow. Firstly, based on the current leaking situation of water supply networks in China and the capability level of China's water management, a water-saving technology integrating PID control and a series of deep learning algorithms was proposed. Secondly, a multi-jet control valve was designed to control pressure and reduce water distribution network cavitation. This technology has been successfully applied in industrial settings in China and has achieved gratifying water-saving results. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) on β-gallium oxide (β-Ga2O3) wafers with various back barrier (BB) materials have garnered considerable attention, mainly due to the superior sheet charge density achieved by the confinement of a large number of electrons in the quantum well, which improves RF performance even further. This work investigates the role of different BB materials of Fe-doped AlGaN buffer AlN/GaN HEMTs on β-Ga2O3 wafers (substrate) with gate–source (LGS) and gate–drain (LGD) distances of 0.4 µm and 1.2 µm, respectively. When compared to traditional substrates such as silicon carbide and silicon, a β-Ga2O3 substrate is more affordable, is accessible in large wafer sizes, and has a lower lattice mismatch (0.4–2.4%) with AlGaN alloys. The effects of gate length scaling (Lg = 50 nm, 100 nm, and 150 nm) on the proposed HEMT devices were also analysed. The short-channel effects can be mitigated by introducing BB structures, which helps avoid further scaling of the barrier layer. With a p-diamond BB of 100 nm thickness, an Fe-doped AlGaN buffer rectangular gated AlN/GaN HEMT Lg = 50 nm results in maximum ID of 5.23 A/mm, gm of 1723 mS/mm, and fT of 361.6 GHz. This superior DC/RF performance can be achieved due to the large confinement of charge carriers into the quantum well and the low leakage current achieved by introducing BB structures and Fe-doped AlGaN buffer. With this outstanding performance, the proposed HEMT device is a promising candidate for next-generation RF applications. [ABSTRACT FROM AUTHOR]

GaN-based enhancement-mode high-electron-mobility transistors (HEMTs) are potential frontrunners for high-frequency power applications due to their simple gate driving circuit and failsafe functioning. A wide range of techniques have been proposed for the fabrication of normally off (E-mode) HEMTs, including recess gate structure, fluorine implantation, P-GaN gate structure, and double/triple gate structure. However, using the above-mentioned techniques, a maximum threshold voltage (Vth) of ~1 V can be achieved, which is not sufficient to prevent faulty operation caused by noise. MIS-HEMTs (metal–insulator–semiconductor HEMT) can facilitate higher positive threshold voltage by capacitance modulation and improve carrier confinement within the two-dimensional electron gas (2DEG), which lowers the gate leakage current. In this paper, different techniques, in particular MIS-HEMT structures, have been studied in detail for normally off operation. [ABSTRACT FROM AUTHOR]

Waste leakage has become a major global concern owing to the negative impacts on aquatic ecosystems and human health. We combine spatial analysis with the Shared Socioeconomic Pathways to project future waste leakage under current conditions and develop mitigation strategies up to 2040. Here we show that the majority (70%) of potential leakage of municipal solid waste into aquatic environments occurs in China, South Asia, Africa, and India. We show the need for the adoption of active mitigation strategies, in particular circular waste management systems, that could stop waste from entering the aquatic ecosystems in the first place. However, even in a scenario representing a sustainable world in which technical, social, and financial barriers are overcome and public awareness and participation to rapidly increase waste collection rates, reduce, reuse and recycling waste exist, it would be impossible to entirely eliminate waste leakage before 2030, failing to meet the waste-related Sustainable Development Goals. The adoption of circular waste management systems is crucial to eliminate land-based waste leakage into aquatic environments. Universal waste collection remains essential. Despite sustainable efforts, fully eliminating waste leakage by 2030 is unfeasible. [ABSTRACT FROM AUTHOR]

In this study, a 3 × 3 blue micro-LED array with a pixel size of 10 × 10 μm2 and a pitch of 15 μm was fabricated on an epilayer grown on a sapphire substrate using metalorganic chemical vapor deposition technology. The fabrication process involved photolithography, wet and dry etching, E-beam evaporation, and ion implantation technology. Arsenic multi-energy implantation was utilized to replace the mesa etching for electrical isolation, where the implantation depth increased with the average energy. Different ion depth profiles had varying effects on electrical properties, such as forward current and leakage currents, potentially causing damage to the n-GaN layer and increasing the series resistance of the LEDs. As the implantation depth increased, the light output power and peak external quantum efficiency of the LEDs also increased, improving from 5.33 to 9.82%. However, the efficiency droop also increased from 46.3 to 48.6%. [ABSTRACT FROM AUTHOR]

Silicon interposers embedded with ultra-deep through-silicon vias (TSVs) are in great demand for the heterogeneous integration and packaging of opto-electronic chiplets and microelectromechanical systems (MEMS) devices. Considering the cost-effective and reliable manufacturing of ultra-deep TSVs, the formation of continuous barrier and seed layers remains a crucial challenge to solve. Herein, we present a novel dual catalysis-based electroless plating (ELP) technique by tailoring polyimide (PI) liner surfaces to fabricate dense combined Ni barrier/seed layers in ultra-deep TSVs. In additional to the conventional acid catalysis procedure, a prior catalytic step in an alkaline environment is proposed to hydrolyze the PI surface into a polyamide acid (PAA) interfacial layer, resulting in additional catalysts and the formation of a dense Ni layer that can function as both a barrier layer and a seed layer, particularly at the bottom of the deep TSV. TSVs with depths larger than 500 μm and no voids are successfully fabricated in this study. The fabrication process involves low costs and temperatures. For a fabricated 530-μm-deep TSV with a diameter of 70 μm, the measured depletion capacitance and leakage current are approximately 1.3 pF and 1.7 pA at 20 V, respectively, indicating good electrical properties. The proposed fabrication strategy can provide a cost-effective and feasible solution to the challenge of manufacturing ultra-deep TSVs for modern 3D heterogeneous integration and packaging applications. [ABSTRACT FROM AUTHOR]

The multiferroic magnetoelectric 2–2 laminated composite systems with BaTiO3 and NiFe2O4 as the ferroelectric and ferrimagnetic phases were successfully fabricated by co-firing technique. For this phase, pure BaTiO3 and NiFe2O4 were successfully synthesized by sol–gel and polyol method, respectively. The structural, microstructural, multiferroic and magnetoelectric coupling properties of phase pure and co-fired systems were investigated using X-ray diffraction, HR-TEM, SEM–EDX, P–E Loop, VSM and magnetoelectric coupling analysis. The multiferroic and magnetoelectric coupling properties of the laminated systems were compared with the mixed system having similar weight percentage of BaTiO3 and NiFe2O4. The fabricated composite systems show good multiferroic and magnetoelectric properties. Compared to mixed composite systems, the laminated structure has an enhanced magnetoelectric (ME) coupling of 6.42 mV/cm.Oe. This variation in ME coupling is attributed to the low leakage current effects in the laminated systems. The ME coupling in the laminates varies with the nature and number of layers. For laminated composite systems, the ME coupling coefficient is found to increase from 6.42 mV/cm.Oe to 10.48 mV/cm.Oe with increase in the number of layers. [ABSTRACT FROM AUTHOR]

The adverse effects of leakage currents and short channel effects (SCE) on mobility degradation in CMOS technology below the 100-nanometer scale. To mitigate these effects, the paper suggests using material engineering techniques to improve the mobility of charge carriers and control SCE effects. Specifically, the switching characteristics of a dual-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are enhanced by stacking the gate with various oxide layers including SiO2, HfO2, and TiO2. These oxide layers possess a range of permittivity capabilities from low to high. By combining different oxide layers the proposed device aims to improve its performance. To evaluate the performance of the proposed device we have employ simulation models such as CONMOB (Concentration Dependent Mobility), AUGER (Auger Recombination), and FLMOB (Field Dependent Mobility). These techniques help to obtain the accurate and reliable simulation results. We have utilized the parameters like drain current, transconductance, electric field, ION, IOFF, and ION/IOFF and simulate them using the Silvaco TCAD tool. The analysis of these parameters are discussed in the paper we have highlighted the compatibility of the proposed DGMOSFET device for low-power applications. In this paper, we have focus on the improving the switching characteristics of a dual-gate MOSFET by utilizing gate stacks with various oxide layers. The proposed device is evaluated through simulations using concentration-dependent mobility, Auger recombination, and field-dependent mobility techniques. The results indicate that the device is suitable for low-power applications. [ABSTRACT FROM AUTHOR]

This work thoroughly investigates the variations in geometrical parameters of both existing Tunnel Field-Effect Transistors (TFETs) and proposed Double-Gate Junctionless Tunnel Field-Effect Transistors (DG-JL-TFETs) to enhance the Radio Frequency (RF) performance of these advanced transistor devices. To improve the RF capabilities of these advanced transistors by employing both qualitative and quantitative research approaches. To overcome the issue of TFET's limited current driving capabilities, which arises from a constrained number of charge carriers tunnelling across the junction, and its ambipolar behaviour (conducting both positive and negative charges), the DG-JL-TFET structure can be proposed as a viable solution. Modifying the attributes of GPVs, such as the gate length ( L g ), channel thickness ( t ch ), and gate oxide thickness ( t ox ), is crucial in the effort to improve RF performance. The qualitative inquiry is an initial stage when a deep understanding of the fundamental principles behind TFET and DG-JL-TFET devices is established. The use of DG-JL-TFETs has led to the achievement of impressive peak frequencies of 217 GHz and 712 GHz. These frequencies demonstrate significant improvements in high-frequency performance, specifically because the realized short circuit gain has reached unity. This achievement is highly dependent on characteristics like transit time. DG-JL-TFETs have a decreased transit time compared to TFETs, which means that charge carriers move more efficiently from the source to the drain area. This results in greater device response and higher operational speed. The incorporation of double-gate (DG) and junctionless (JL) designs improves gate control, resulting in reduced leakage current and enhanced on-state current. DG-JL-TFETs, in contrast to TFETs, possess a broader tunnelling zone and do not have a PN junction. The specific arrangement of this structure allows for a greater frequency of electron tunnelling across the junction, as seen by the notably increased current in the on-state, measuring 5.7 × 10 - 3 A, which exceeds TFET's current of 16.13 × 10 - 6 A. [ABSTRACT FROM AUTHOR]

Cascaded multilevel inverters render higher output voltage, allowing for grid power injection without the use of booster transformers. Large leakage current is produced by voltage across parasitic capacitance in transformerless cascaded multilevel inverters (CMLIs) used mostly for solar photovoltaic sources. This voltage depends on the control law, modulation and inverter topology. To resolve leakage currents, numerous alternatives have emerged, which would include new converter topology, modulation methods, and control techniques. The AC signal of the requisite voltage for power injection into the grid is generated by CMLIs without the use of an additional boost stage. With lower total harmonic distortion and smaller filters, this additional benefit enhances the overall performance of PV systems. Various redesigned circuit architecture is recommended for transformerless operation because traditional CMLIs need additional switches. This work describes a new generalized circuit design named as X10 inverter for removing leakage current in an asymmetric lowered switch count cascaded multilevel inverter. The proposed approach employs two switches, one on each side of the DC sources. This insertion automatically disconnects the sources from the load, resulting in a lower common mode voltage transition and the elimination of leakage current. Inverters with any number of output voltage levels and sources can use the proposed technique. The proposed topology's efficacy in lowering leakage current and improving topology efficiency is evaluated using simulation and experimental setup. [ABSTRACT FROM AUTHOR]

The conditions for the growth of n-type Ge layers with the parameters required to create a Ge-MISFET with an induced p-type channel using the hot wire chemical vapor deposition (HW CVD) method are determined. The conditions for deposition using electron beam deposition and subsequent annealing of the subgate high-k dielectric ZrO2:Y2O3 layers are optimized, allowing us to achieve a leakage current value of 5 × 10–6 A/cm2. For the developed device structure, some parameters of the Ge-MISFET are calculated, such as the channel length, maximum voltage between the sink and source, and breakdown voltage. [ABSTRACT FROM AUTHOR]

Platinum oxide (PtOx) Schottky contacts on degenerately doped β-Ga2O3 substrates show an increased barrier height of 85% and 64% when compared to nickel and platinum Schottky contacts, respectively. At low reverse voltage bias, the reverse leakage current of the PtOx Schottky barrier diodes was approximately 5–6 orders of magnitude lower than the reference evaporated Ni and Pt Schottky contacts. PtOx Schottky contacts were deposited using reactive sputtering on highly doped (8 × 1018 cm−3) ( 2 ¯ 01 ) β-Ga2O3:Sn substrates grown by the edge-defined film-fed growth (EFG) method. All Schottky metals were capped with evaporated Au. Capacitance–voltage and temperature-dependent current–voltage measurements were performed in order to extract the barrier height of the PtOx Schottky contact. Analysis of the diode ideality factors reveal that the PtOx Schottky contacts on highly doped β-Ga2O3 do not follow the thermionic field emission model and are impacted by inhomogeneous barrier height distribution. This work highlights the significance of PtOx Schottky contacts for β-Ga2O3-based power devices as a means for reducing leakage current. This work also holds relevance for low-voltage applications, where Schottky contacts for degenerately doped semiconductors can enable new electronic device applications. [ABSTRACT FROM AUTHOR]

The semiconductors industry has put its eyes on two-dimensional (2D) materials produced by chemical vapour deposition (CVD) because they can be grown at the wafer level with small thickness fluctuations, which is necessary to build electronic devices and circuits. However, CVD-grown 2D materials can contain significant amounts of lattice distortions, which degrades the performance at the device level and increases device-to-device variability. Here we statistically analyse the quality of commercially available CVD-grown hexagonal boron nitride (h-BN) from the most popular suppliers. h-BN is of strategic importance because it is one of the few insulating 2D materials, and can be used as anti-scattering substrate and gate dielectric. We find that the leakage current and electrical homogeneity of all commercially available CVD h-BN samples are significantly worse than those of mechanically exfoliated h-BN of similar thickness. Moreover, in most cases the properties of the CVD h-BN samples analysed don't match the technical specifications given by the suppliers, and the sample-to-sample variability is unsuitable for the reproducible fabrication of capacitors, transistors or memristors in different batches. In the short term, suppliers should try to provide accurate sample specifications matching the properties of the commercialized materials, and researchers should keep such inaccuracies in mind; and in the middle term suppliers should try to reduce the density of defects to enable the fabrication of high-performance devices with high reliability and reproducibility. Large-scale 2D hexagonal boron nitride (hBN) grown via chemical vapour deposition (CVD) has strategic importance for various applications of 2D materials. Here, the authors analyse the structural and electrical properties of commercially available CVD hBN from 9 popular suppliers and compare the results with mechanically exfoliated hBN and in-house CVD hBN. [ABSTRACT FROM AUTHOR]

Low-temperature amorphous thin films with excellent energy storage properties play a crucial role in silicon-based microelectronic applications. The (1-x)Sr0.925Bi0.05TiO3-xBiMg0.5Ti0.5O3 (SBT-BMT) (x = 0, 0.1, 0.2, 0.3) amorphous films were prepared on Pt/Ti/SiO2/Si substrates by chemical solution deposition in order to achieve high energy storage performance. The X-ray diffractometer results show that amorphous films were successfully fabricated. The addition of BMT can results in a reduction of the crystallization temperature for the SBT film, and this can be used to obtain an critical amorphous state for the 0.9SBT-0.1BMT film, where the dielectric constant increases significantly and the leakage current is the minimum. The final 0.9SBT-0.1BMT film exhibited a recoverable energy storage density of 32 J/cm3 and an energy storage efficiency of 78% at an electric field of 4097 kV/cm. Furthermore, the energy storage performance remained stable over the temperature range of 20 ~ 200 °C, the frequency range of 2 ~ 10 kHz, and even after 107 electrical cycles. It is expected to provide new strategy to optimize the energy storage performance of dielectric capacitors. [ABSTRACT FROM AUTHOR]

The current–voltage and capacitance–voltage characteristics of InGaAs/InP heterostructure p-i-n photodiodes fabricated by mesa technology have been studied. Photodiodes of circular configuration differ in active region diameter from 0.05 to 2.5 mm. All measurements are performed in the dark at room temperature using the probe method on a wafer with ready-made devices. Data are obtained on dark currents (leakage currents), Idark, which are interpreted in terms of the surface and bulk currents in p–i–n photodiodes of various sizes. In the absorbing layer of the InGaAs/InP photodiode heterostructures, the concentration profiles ND(x) are assessed for the first time by the nondestructive CV method and are compared with the electrochemical profiling data. It is shown that for the most part of the heterostructure i-layer the two methods are complementary. [ABSTRACT FROM AUTHOR]

In this study, a three-level static RAM cell with a single BL based on 16 nm BWG CNFET technology is proposed for use in high-performance IoT platforms. The proposed memory structure in a bit-interleaved architecture compatible design consists of a standard triple buffer gate (STB) based on the BWG CN-TGDI method and a pair of transmission gates as an access network. In the STB cell structure, the threshold voltage calibration by the flat band voltage parameter of the CNTs has been used to improve the static noise margin at logic level '1'. In addition, pseudo-resistor and stacked transistor structures have been used to control the single static current path during logic level '1' generation and cell leakage current, respectively. The simulation results based on the Monte Carlo method show that the hardware performance parameters PDP and EDP for the proposed design have been improved by 38.8% and 31%, respectively, compared to the counterpart structure. Moreover, the proposed architecture has shown a more reasonable result in terms of noise immunity than the best-performing design by 1.93 times. Finally, to investigate a real-world application, the triple memory structure has been used to store the colored QR code image with the data content of three values using the proposed hardware algorithm. The obtained results for the quality evaluation metrics, PSNR and MSSIM, emphasize the suitability of the proposed memory architecture for the development of next-generation SoCs. [ABSTRACT FROM AUTHOR]

In this paper, an all-digital, 10-bit, low-power Time-to-Digital Converter (TDC) is proposed for use in biomedical applications. To reduce the area and power consumption, as well as provide noise shaping capability, the Gated Ring Oscillator (GRO) architecture is chosen as the core for the proposed TDC. Regarding the problems created by the leakage current in GROs, especially in low-frequency applications, a new approach for data capturing is used. The proposed modified data capturing method tackles the leakage current effect and allows the TDC to operate at ultralow frequencies. The proposed TDC achieves a dynamic range of 1.76 µs, and the resolution of 1.76 ns at 1KS/s sampling frequency. Simulations were performed using the 0.13 µm CMOS process. The TDC power consumption was 45.85 nW at a 0.4 V supply and the Signal to Noise and Distortion Ratio (SNDR) was 54.55 dB. [ABSTRACT FROM AUTHOR]