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The demand for high-performance electromechanical resonators is ever-growing across diverse applications, ranging from sensing and time-keeping to advanced communication devices. Among the electromechanical materials being explored, thin-film lithium niobate stands out due to its strong piezoelectric properties and low acoustic loss. However, in nearly all existing lithium niobate electromechanical devices, the configuration is such that the electrodes are in direct contact with the mechanical resonator. This configuration introduces an undesirable mass-loading effect, producing spurious modes and additional damping. Here, we present an electromechanical platform that mitigates this challenge by leveraging a flip-chip bonding technique to separate the electrodes from the mechanical resonator. By offloading the electrodes from the resonator, our approach yields a substantial increase in the quality factor of these resonators, paving the way for enhanced performance and reliability for their device applications. [ABSTRACT FROM AUTHOR]

Hydraulic technology with smaller sizes and higher reliability trends, including fault prediction and intelligent control, requires high-performance temperature and pressure-integrated sensors. Current designs rely on planar wafer- or chip-level integration, which is limited by pressure range, chip size, and low reliability. We propose a small-size temperature/high-pressure integrated sensor via the flip-chip technique. The pressure and temperature units are arranged vertically, and the sensing signals of the two units are integrated into one plane through silicon vias and gold–gold bonding, reducing the lateral size and improving the efficiency of signal transmission. The flip-chip technique ensures a reliable electrical connection. A square diaphragm with rounded corners is designed and optimised with simulation to sense high pressure based on the piezoresistive effect. The temperature sensing unit with a thin-film platinum resistor measures temperature and provides back-end high-precision compensation, which will improve the precision of the pressure unit. The integrated chip is fabricated by MEMS technology and packaged to fabricate the extremely small integrated sensor. The integrated sensor is characterised, and the pressure sensor exhibits a sensitivity and sensitivity drift of 7.97 mV/MPa and −0.19% FS in the range of 0–20 MPa and −40 to 120 °C. The linearity, hysteresis, repeatability, accuracy, basic error, and zero-time drift are 0.16% FS, 0.04% FS, 0.06% FS, 0.18% FS, ±0.23% FS and 0.04% FS, respectively. The measurement error of the temperature sensor and temperature coefficient of resistance is less than ±1 °C and 3142.997 ppm/°C, respectively. The integrated sensor has broad applicability in fault diagnosis and safety monitoring of high-end equipment such as automobile detection, industrial equipment, and oil drilling platforms. [ABSTRACT FROM AUTHOR]

In this work, Sn-0.7Cu-WO3 nanomodified solders were electrodeposited from an aqueous acidic plating bath containing various fractions of WO3 nanoparticles (0.1, 0.25, 0.5 wt%) NPs for mini-light emitting diodes (mini-LEDs) packaging. The produced nanomodified solders were characterized for their morphology, microhardness, melting point, and electrical resistivity. Further, the nanomodified solder bumps were used to mount a 1608 mini-LED chip/ENIG (Electroless Nickel Immersion Gold) pad by reflowing at 240 °C in the air. High-temperature aging was done at 125 °C for 144, 256, and 400 h and joint shear tests were performed to examine the interfacial properties and growth kinetics of the soldered mini-LED/Sn-0.7Cu-WO3/ENIG joints. The results indicated the formation of (Ni,Cu)3Sn4 intermetallic compounds (IMCs) across the solder/ ENIG pad joint. The thickness of the IMC layer decreases showing the maximum rate of decrease when the composition is Sn-0.7Cu-0.25WO3. It was concluded that the optimal set of microstructure, melting point, electrical resistivity, and joint shear reliability could be achieved when the nanomodified solder is reinforced with 0.25 wt.% WO3 NPs into Sn-0.7Cu matrix and thus it can be a potential contestant for the upcoming applications in mini-LED packaging. [ABSTRACT FROM AUTHOR]

Recent years have witnessed significant advancements in deep learning-based 3D object detection, leading to its widespread adoption in numerous applications. As 3D object detectors become increasingly crucial for security-critical tasks, it is imperative to understand their robustness against adversarial attacks. This paper presents the first comprehensive evaluation and analysis of the robustness of LiDAR-based 3D detectors under adversarial attacks. Specifically, we extend three distinct adversarial attacks to the 3D object detection task, benchmarking the robustness of state-of-the-art LiDAR-based 3D object detectors against attacks on the KITTI and Waymo datasets. We further analyze the relationship between robustness and detector properties. Additionally, we explore the transferability of cross-model, cross-task, and cross-data attacks. Thorough experiments on defensive strategies for 3D detectors are conducted, demonstrating that simple transformations like flipping provide little help in improving robustness when the applied transformation strategy is exposed to attackers. Finally, we propose balanced adversarial focal training, based on conventional adversarial training, to strike a balance between accuracy and robustness. Our findings will facilitate investigations into understanding and defending against adversarial attacks on LiDAR-based 3D object detectors, thus advancing the field. The source code is publicly available at https://github.com/Eaphan/Robust3DOD. [ABSTRACT FROM AUTHOR]

Despite significant progress made over the past decade in thermally activated delayed fluorescence (TADF) molecules as a material paradigm for enhancing the performance of organic light-emitting diodes, the underlying spin-flip mechanism in these charge-transfer (CT)-type molecular systems remains an enigma, even since its initial report in 2012. While the initial and final electronic states involved in spin-flip between the lowest singlet and lowest triplet excited states are well understood, the exact dynamic processes and the role of intermediate high-lying triplet (T) states are still not fully comprehended. In this context, we propose a comprehensive model to describe the spin-flip processes applicable for a typical CT-type molecule, revealing the origin of the high-lying T state in a partial molecular framework in CT-type molecules. This work provides experimental and theoretical insights into the understanding of intersystem crossing for CT-type molecules, facilitating more precise control over spin-flip rates and thus advancing toward developing the next-generation platform for purely organic luminescent candidates. Kim et al. propose a model for the complex spin-flip process in charge-transfer-type thermally activated delayed fluorescence molecules, uncovering the origin of the high-lying triplet state, addressing a pressing issue discussed over the last decade. [ABSTRACT FROM AUTHOR]

This paper aims to develop a thermal fluid–structure interaction (FSI) methodology to study the effect of different Cu pillar bump diameters on thermal and mechanical performance during the reflow soldering process. The desktop reflow oven is modeled in ANSYS FLUENT, while the ball grid array (BGA) package assembly is modeled in ANSYS STATIC STRUCTURAL. The accuracy of the simulated reflow temperature profile has been verified by comparing it with the experimental temperature data, according to JEDEC standards. The temperature distributions of solder and Cu pillar bumps are compared. A parametric study has been conducted to analyze the effect of different Cu pillar diameters on the reflow soldering process. By coupling the thermal loads with the structural analysis using thermal FSI, Cu pillar bumps with a diameter of 0.20 mm are found to exhibit the lowest reflow temperature, minimum temperature difference, and minimum deformation and thermal stress, making them the most suitable interconnection joints for flip chip technology. The study also examines the effect of soldering materials on the Cu pillar bump. The findings of this research provide valuable insights into the effects of varying Cu pillar diameters on the reflow soldering process, which can help in the development of more reliable electronic assemblies. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of various copper (Cu) pillar bump heights on temperature distribution, deformation and thermal stress during reflow. The virtual reflow oven environment was simulated using the fluid domain of the oven model. The accuracy of the fluid analysis was verified by comparing the obtained results with experimental data, which was conducted based on the Joint Electron Device Engineering Council (JEDEC) Standard. In addition, a grid independence test was carried out on the fluid mesh to determine the optimal mesh size for the simulations. A thermal fluid–structure interaction (FSI) approach was employed to couple the thermal results from the fluid analysis with the solid assembly. The results of the coupling analysis revealed that Cu pillar bumps with a height of 0.09 mm exhibited the lowest reflow temperature, minimal maximum deformation, and thermal stress, indicating that it is the optimal potential height for forming a good joint. The study also examines the impact of soldering materials, such as tin-bismuth (SnBi) and tin-silver-copper solder alloys (SAC305 and SAC405), on the Cu pillar bump. This study enables a comprehensive analysis of the thermal and mechanical performance of different Cu pillar bump parameters during the reflow process. [ABSTRACT FROM AUTHOR]

The reliability of flip-chip packages is significantly impacted by the type of packaging materials, such as underfill, solder, flux, and solder mask. Underfill reduces the coefficient of thermal expansion (CTE) mismatch between the semiconductor chip and printed circuit board, thereby minimizing the chances of thermal fatigue failure of the package. There are a plethora of underfill suppliers and selecting the most suitable underfill for preparing a flip-chip package is critical as there are conflicting criteria. These criteria are limited to glass transition temperature (Tg), CTE, elastic modulus (E), coefficient of moisture expansion, fracture toughness (Kic), shear strength, and flowability. Choosing appropriate alternatives based on the above conflicting criteria is basically a multi-criteria problem. This research proposes a grey simplified best–worst method (GSBWM) to identify the criteria weight. The proposed method has less calculation complexity than the previous grey best–worst methods, and it does not need operations research and modeling knowledge, and optimization software to solve it. The accuracy of the GSBWM is investigated using three data sets. The results showed the high accuracy of the proposed method in all data sets. This study employed the combination of GSBWM and a grey possibility degree based method to select the most suitable underfill material for reliable flip-chip packages as a real-world problem. [ABSTRACT FROM AUTHOR]

In this work, rapid failure of a few minutes was observed in real ball grid array solder joints under high current density (8 × 103 and 1 × 104 A cm−2) at room temperature. For each test condition, the failure solder joint was detected at the same position of the daisy chain by computed tomography technology. Furthermore, the open failure for all solder joints was caused by the chip side (anode side) Cu dissolution. Microstructure evolution for a pair of electrically connected solder joints was investigated. In both solder joints, Cu atoms on the chip side were dissolved to the board side with the formation of intermetallic compound particles in solder matrix. Finite element simulation was introduced to calculate the current density, temperature, and heat flux distribution. The temperature gradient along the direction of Cu migration in solder joint was developed due to the accumulation of Joule heating. Thermomigration was confirmed as the dominant mechanism of chip side Cu dissolution. [ABSTRACT FROM AUTHOR]

This paper examines the thermal resistance of the mid-infrared "flip-chip" LEDs based on the p‑InAsSbP/n-InAsSb heterostructure. It was shown that the measurement of thermal resistance via a thermal control unit (forward p–n junction voltage) for LEDs based on narrow-gap semiconductors must be carried out at low temperature when thermal control unit is constant. [ABSTRACT FROM AUTHOR]

The magnetic properties of permalloy-based trilayers of the form Py0.8Cu0.2/Py0.4Cu0.6/Py/IrMn were studied as the spacer layer undergoes a paramagnetic to ferromagnetic phase transition. We find the coupling between the free Py0.8Cu0.2 layer and the exchange bias pinned Py to be strongly temperature-dependent: there is negligible coupling above the Curie temperature of the Py0.4Cu0.6 spacer layer, strong ferromagnetic coupling below that temperature, and a tunable coupling between these extremes. Polarized neutron reflectometry was used to measure the depth profile of the magnetic order in the system, allowing us to correlate the order parameter with the coupling strength. The thickness dependence shows that these are interface effects with an inverse relationship to thickness, and that there is a magnetic proximity effect that enhances the Curie temperature of the spacer layer with characteristic length scale of about 7 nm. As a demonstration of potential functionality of such a system, the structure is shown to spontaneously flip from the antiparallel to parallel magnetic configuration once the spacer layer has developed long-range magnetic order. [ABSTRACT FROM AUTHOR]

Covalent organic frameworks (COFs) have been attracting intense research due to their permanent porosity, designable architecture, and high stability. However, COFs are challenging to crystallize and their synthesis often results in tiny crystal sizes and low crystallinities, which hinders an unambiguous structure determination. Herein, we demonstrate that the structure of low-crystallinity COF Py-1P nanocrystals can be solved by coupling three-dimensional electron diffraction (3DED) with simulated annealing (SA). The resulting model is comparable to that obtained from high-crystallinity samples by dual-space method. Moreover, for low-resolution 3DED data, the model obtained by SA shows a better framework than those provided by classic direct method, dual-space method, and charge flipping. We further simulate data with different resolutions to understand the reliability of SA under different crystal quality conditions. The successful determination of Py-1P structure by SA compared to other methods provides new knowledge for using 3DED to analyze low-crystallinity and nanosized materials. Covalent organic frameworks have demonstrated promise for a wide variety of applications, but their synthesis often results in materials with low crystallinity that are challenging to characterize. Here, coupling three dimensional electron diffraction with simulated annealing is shown to enable the structural determination of a low crystallinity pyrene-containing covalent organic framework. [ABSTRACT FROM AUTHOR]

The integrity of solder joints of components in an electronic device is critical to the device reliability. The miniaturisation trend in the development of electronic products has continued to challenge the shear strength of the solder joints in these devices and necessitates implementation of optimal reflow profiles to achieve maximum joint strength. This study proposes an optimal parameter combination of reflow profile factors which demonstrate potential for delivering maximum shear strength of solder joints. The Taguchi design of experiment (DoE) is employed to generate eight orthogonal array designs of L24 reflow profiles. The factors/parameters investigated are preheat gradient, time above liquidus (TAL), peak temperature and cooling rate. Three test vehicles of varying solder joint sizes are made from R1206, R0805 and R0603 resistors. Reflow profile number 3 constituting 1.2°C/s preheat, 45 s TAL, 245°C peak temperature and 60% cooling rate is optimal because it yielded joints with the highest strength and ca. 4 µm intermetallic compound thickness. The solder joint shear strength decreased with a decrease in the size of the lead-free joint irrespective of the reflow profile implemented. These results will be useful for electronic packaging and reliability engineers faced with challenges of improving device operational mechanical performance in the continuing trend of product miniaturisation. [ABSTRACT FROM AUTHOR]

Second-generation voltage conveyor structures, based on the employment of flipped voltage follower stages, are investigated and proposed in this work. The proposed core has the feature of offering extremely low or electronically adjustable input resistance and programmable outputs, enhancing the achieved design flexibility and versatility of this active cell. Two design examples are presented in this work, including a multi-phase sinusoidal oscillator topology and an electronically adjustable first-order low-pass filter, both supported by simulation and experimental results. [ABSTRACT FROM AUTHOR]

the thermal characteristics of SiC/Si samples obtained by the method of coordinated substitution of atoms at different thicknesses of SiC have been experimentally investigated. It has been found that for SiC thicknesses less than 200 nm, the thermal resistance of SiC/Si is approximately equal to 2 K/W, which is the same as for pure silicon substrate. Such samples will perfectly remove heat from the light-emitting heterostructure grown on SiC/Si. With an increase in the thickness of SiC, the SiC film is detached, which leads to a loss of thermal contact between SiC and Si. The thermal resistance increases at the same time by more than two orders of magnitude. The ability to remove easily the opaque part of the substrate can form the basis of the technology for manufacturing flip-chip LED. [ABSTRACT FROM AUTHOR]

Silicon photonics has emerged as a mature technology that is expected to play a key role in critical emerging applications, including very high data rate optical communications, distance sensing for autonomous vehicles, photonic-accelerated computing, and quantum information processing. The success of silicon photonics has been enabled by the unique combination of performance, high yield, and high-volume capacity that can only be achieved by standardizing manufacturing technology. Today, standardized silicon photonics technology platforms implemented by foundries provide access to optimized library components, including low-loss optical routing, fast modulation, continuous tuning, high-speed germanium photodiodes, and high-efficiency optical and electrical interfaces. However, silicon's relatively weak electro-optic effects result in modulators with a significant footprint and thermo-optic tuning devices that require high power consumption, which are substantial impediments for very large-scale integration in silicon photonics. Microelectromechanical systems (MEMS) technology can enhance silicon photonics with building blocks that are compact, low-loss, broadband, fast and require very low power consumption. Here, we introduce a silicon photonic MEMS platform consisting of high-performance nano-opto-electromechanical devices fully integrated alongside standard silicon photonics foundry components, with wafer-level sealing for long-term reliability, flip-chip bonding to redistribution interposers, and fibre-array attachment for high port count optical and electrical interfacing. Our experimental demonstration of fundamental silicon photonic MEMS circuit elements, including power couplers, phase shifters and wavelength-division multiplexing devices using standardized technology lifts previous impediments to enable scaling to very large photonic integrated circuits for applications in telecommunications, neuromorphic computing, sensing, programmable photonics, and quantum computing. [ABSTRACT FROM AUTHOR]

Fabrication and subsequent on-chip direct current characterization are reported for a vertical-mesa avalanche transit time (ATT) diode. The active region of such diodes consists of a GaN/AlGaN heterostructure. The study has shown that the device has the potential to develop 1 × 10 11 W / m 2 RF power at 0.1 THz. An indigenously developed strain-corrected mixed quantum tunneling drift-diffusion (Sc-MQTDD) device simulator has been used for the pre-fabrication design of an ultra-wide band gap (UWBG) III-V semiconductor-based device, and, through performance comparison, the validity of the model has been successfully established. The simulator incorporates relevant aspects of device physics, including strain-induced conduction band modification, subsequent piezoelectric polarization, variation of effective mass, and quantum mechanical tunneling for heterostructures to solve the Schrodinger equation, subject to appropriate modified boundary conditions. Furthermore, a set of studies were carried out to investigate the effects of the mesa orientation/growth plane on the power frequency behavior of III–V devices. Finally, a laterally oriented AlGaN/GaN/AlGaN heterostructure high electron mobility ATT (HEMATT) diode with a two-dimensional electron gas (2-DEG) active region is proposed. The device performance has been estimated using the in-house quantum simulator. To the best of the authors' knowledge, this aspect of the study is reported for the first time in this paper. Electrical characteristics of the designed HEMATT oscillator yielded a very low parasitic resistance ∼ 7.3 × 10 - 10 Ω m - 2 compared to its vertical-device counterpart. This is due to the significant mobility enhancement in the 2-DEG active region. Consequently, high output power ~ P D S HEMATT = 1.5 × 10 11 W / m 2 has been obtained at a high operating frequency ~ 0.4THz. [ABSTRACT FROM AUTHOR]

The current trend of electrical devices development is progressing towards miniaturization, multi-function and high density, device integration and fine pitch in a smaller package size. This led to the invention of copper pillar bumps which acts as a connection between the dies to its corresponding substrate, which allows the fabrication of smaller semiconductor devices. The dies were mounted onto the substrate by undergoing mass reflow process where the SAC305 solder from the copper pillar bumps and substrate bumps will melt together and solidify to form a solder joint. The quality of the solder joint is influenced by the parameters that govern the reflow profile, which are ramp rate, soak time, time above liquidus time, peak temperature and cooling rate. If the reflow profile is not properly optimized, defects such as voids in the solder joint can pose a reliability issue for the packaged unit. Therefore, in this paper, ramp rate, soak time and time above liquidus of reflow profiles for die utilizing copper pillar bumps with SAC305 as its solder material was studied and optimized in finding the recommended range of each parameter of the reflow profiles that yield the least voiding in the solder joint. The experiment was conducted by varying the reflow profile parameter which are ramp rate, soak time and time above liquidus, which the solder joint cross section and X-ray images were then analysed to study its influences. Additional experiment that investigates flux outgassing rate of different flux activity levels and the influence of component standoff height and mis-alignment offset towards solder-creeping defect were conducted in this article. [ABSTRACT FROM AUTHOR]

The method of introducing ultrasonic action was used to bond the flip chip with copper pillar solder joints, and the influence of ultrasonic vibration on the structure evolution and mechanical properties of the solder joint was studied. The three-dimensional finite element analysis method was used to simulate the vibration distribution of the chip and the sound pressure distribution in the solder joints. The results indicate that the introduction of ultrasound will cause the intermetallic compound (IMCs) at the upper interface of the solder joint to be broken and thin, and the IMCs at the lower interface will grow and thicken on the original basis. At the same time, the shear strength of the solder joints first increases and then decreases with the increase of the ultrasonic power, and has little relationship with the ultrasonic action time. The introduction of ultrasound in the middle stage of the bonding process will increase the strength of the solder joint, and, in the final stage of the bonding process, will cause larger cracks in the solder joints, which will affect their strength. Simultaneously, the simulation results show that the amplitude at the edge of the upper surface of the chip is larger than that in the middle, and that the sound pressure of the solder joints at the boundary is larger than that of the middle solder joints. [ABSTRACT FROM AUTHOR]

An electret refers to a permanent electric dipole. Nonconductive electrets (polymers and ceramics) have long been studied and utilized, but conductive electrets (metals and carbons) are emerging. This paper introduces the concept of the electret-based capacitance C′ to elucidate the discharge behavior of conductive electrets in the form of unpoled solder and other conductors (metals). The C′ is defined as the electret charge Q′ (determined by integrating the discharge curve) divided by the DC electret voltage V′. The conventional permittivity-based capacitance C (measured) is lower than C′ by orders of magnitude. For Sn–4Ag lead-free solder, C′ (given by Q′/V′) is 620 F, whereas C is 175 pF. The electret stems from the interaction of a small fraction of the carriers (free electrons) with the atoms, as supported by DC polarization asymmetry. For Sn–4Ag, this fraction is 3.5 × 10–9. Electret discharge (V′ decreasing to zero) occurs upon short circuiting. Self-charge (V′ restored) occurs upon subsequent open circuiting, being slightly more sluggish than discharge. The electret discharge/charge amounts to discharge/charge of C′. The discharge/charge time constant is found to approximately equal RC′ (R = resistance) and the discharge/charge energy is found to approximately equal ½ C′V′2, as expected for the discharge/charge of C′ and shown for Sn–4Ag, copper (0 and 37% cold work) and low-carbon steel. This two-fold agreement between theory and experiment for each of the metals studied strongly supports the C′ concept. Strong correlation occurs among high fraction of carriers that participate, high participating charge density and high discharge time constant. [ABSTRACT FROM AUTHOR]

We describe an indium bump process applicable to our low-temperature detectors and associated readout. A titanium nitride under bump metallization layer is reactively sputtered onto wiring pads as a diffusion barrier and adhesion layer. Indium is thermally evaporated onto this layer at the desired thickness for bump bonding. Patterning for both titanium nitride and indium layers is accomplished by liftoff techniques. The process flow is compatible with many processes utilized for the fabrication of low-temperature detectors and other superconductive devices. [ABSTRACT FROM AUTHOR]

Josephson junctions based on semiconductor nanowires are potential building blocks for electrically tunable qubit structures, e.g., the gatemon or the Andreev qubit. However, an actual realization requires the thorough investigation of the intrinsic excitation spectrum. Here, we demonstrate the fabrication of low-loss superconducting microwave circuits that combine high quality factors with a well-controlled gate architecture by utilizing a flip-chip approach. This platform is then used to perform single-tone and two-tone experiments on Andreev states in in-situ grown InAs/Al core/half-shell nanowires with shadow mask defined Josephson junctions. In gate-controlled and flux-biased spectroscopic measurements we find clear signatures of single quasiparticle as well as quasiparticle pair transitions between discrete Andreev bound states mediated by photon-absorption. Our experimental findings are supported by simulations that show that the junction resides in the intermediate channel length regime. Josephson junctions, comprised of semiconducting nanowires, can be used to design qubit architectures but for the successful application, it is necessary to study their intrinsic excitation spectrum. Here, the authors adapt a flip-chip method to realize superconducting microwave circuits and perform spectroscopy of Andreev bound states in mesoscopic InAs/Al core/shell nanowire Josephson junctions. [ABSTRACT FROM AUTHOR]

The investigation of three-dimensional magnetic textures and chirality switching has attracted enormous interest from the perspective of fundamental research. Here, the three-dimensional magnetic structures of skyrmion bubbles in the centrosymmetric magnet MnNiGa were reconstructed with the vector field tomography approach via Lorentz transmission electron microscopy. The magnetic configuration of the bubbles was determined based on the reconstructed magnetic induction (B-field) at their surfaces and centers. We found that the bubbles easily switched their chirality but preserved their polarity to retain their singularity in the matrix of the material. Our results offer valuable insights into the chirality behavior of skyrmion bubbles. Skyrmion bubbles consist of a centre magnetization pointing up or down, and a swirling vortex magnetic texture, either clockwise or anticlockwise around this. Here, Yao et al use a three-dimensional imaging approach to study this magnetic texture, and show that while the in-plane vortex-like texture changes easily, the centre magnetic direction, the polarity, is retained, leading to a reversed chirality. [ABSTRACT FROM AUTHOR]

The micro bump is an element for connecting and stacking the silicon die of a semiconductor device, and any damage to the micro bump can greatly influence the reliability of the semiconductor. A shear test and analysis were performed to investigate the effect of the micro bump structure and shear speed on the failure mode, and a structural improvement was proposed. The failure mode and reaction force of the micro bump were measured through shear tests of four micro bump structures with a diameter of 25 μ m at two shear speeds using a bond tester. In addition, a finite element model simulating the shear test was developed using ANSYS and was analyzed under the same conditions as the shear test. It was confirmed that tungsten via has a resistance effect on shear force. Additionally, a structural improvement of the micro bump to resist shear force was suggested by analyzing the passivation thickness and bottom diameter of the micro bumps as design variables. [ABSTRACT FROM AUTHOR]

A low output impedance voltage buffer for the design of flipped voltage follower (FVF) based low drop out (LDO) regulator usually assists in maintaining better stability and fast transient response. An adaptive source follower with very low output impedance is presented for driving gate of bulky pass element in the FVF based output stage of the LDO for faster recovery during load transients. Based on the buffer, a fast response (280 ps Approximately) output capacitor less LDO capable of driving 10's of pF to 1 nF capacitive loads while maintaining enough phase margin is proposed. The LDO is verified with simulation in 45 nm CMOS process, 1.2 V supply. The LDO offers stable regulation over range from 200 µA to 30 mA with regulated DC voltage of 1.1 V. with quiescent current of 36 µA. During the load transition of 200 µA → 30 mA with 10 ns edge time, the recovery time of 37 ns under typical conditions is achieved with overshoot of 93 mV and undershoot of 122 mV. The transient performance is also verified against wider loads as large as 10 pF–1 nF. The worst case deviation from the regulated output for various process corner variations are within 2 % of nominal 1.1 V. The simulated PSR is - 22 dB over the band of 1–100 kHz for heavy load current of 30 mA, - 15.5 dB for light load current of 200 µA. The proposed LDO achieves an overall efficiency of 78.4 % [ABSTRACT FROM AUTHOR]

This paper presents an experimental investigation and a finite element (FE) analysis study on the thermal and mechanical behaviors of insulated-gate bipolar transistor (IGBT) power modules under various operating conditions. The power cycling test conditions are provided by two test benches, a direct current (DC) test bench and a pulse width modulation (PWM) test bench. Infrared (IR) camera acquisition methods are suggested as an approach for transient temperature measurements to estimate the effects of operating conditions and switching frequency on the thermal performance of an IGBT module. An electrical–thermal–mechanical FE model of an IGBT module is employed to determine the stress in the interconnections of an IGBT module induced by junction temperature fluctuations. Results indicate that the operating conditions significantly impact the maximum junction temperature, the junction temperature increase rate, and the junction temperature distribution of an IGBT chip and the thermally induced stress in the interconnections. The switching frequency strongly impacts the junction temperature of an IGBT chip, and the maximum junction temperature increases when the switching frequency increases due to the increasing switching loss. Furthermore, the junction temperature variation induced by the instantaneous switching loss is estimated by the proposed IR camera measurement method. [ABSTRACT FROM AUTHOR]

A novel double gates flip-structure enhancement-mode (E-mode) high electron mobility transistor with step field plate (DFF HEMT) is proposed. It features face-to-face double gates, including a top trench MIS gate with a step field plate and a bottom planar MIS gate, which is shorted together. In the on-state, the double gates not only can restore the 2DEG by the higher electric potential, but also can form the electron accumulation layers, and thus increase the saturation output current and reduce the on-resistance. The face-to-face double gates together deplete the 2DEG by using the work function difference to realize E-mode, instead of by etching the AlGaN layer under the gate for the conventional MIS gate E-mode HEMT. The double-gate structure not only avoids etch damage, but also maintains both high threshold voltage and low on-resistance. Meanwhile, the step gate field plate modulates E-field distribution to increase the BV. In order to easily fabricate, the trench gate with step field plate must be located on the top of device, forming the flip-structure. The flip-structure is also beneficial to decrease the leakage current in the substrate. The simulated Vth, BV and Id of the DFF HEMT are 0.8 V, 465 V and 494 mA/mm, respectively. The FOM of the DFF HEMT is 79.8% and 444.2% higher than those of the conventional MIS-FP HEMT and MIS HEMT. [ABSTRACT FROM AUTHOR]

This paper reviewed the state-of-art copper pillar technology in flip-chip packaging, driven by the semiconductor industry's demands for thinner and faster data transmission. This technology with area array feature is a surface mount technology process used to form interconnection bonding between ball grid array chip and printed circuit board (PCB) by the reflow soldering process. The conversion of the flip-chip interconnection bump from the solder ball to the Cu pillar bump with the solder cap and the joint performance within the reflow oven are presented in this review. The simulation tools have recently facilitated the Cu pillar bump research during the PCB assembly process. Thus, this review focuses on the simulation modeling of the PCB assembly within a reflow oven using different numerical approaches. The thermal and air flow aspects of the reflow process are reviewed. The temperature distribution and the thermal stress condition of the PCB assembly within the reflow oven are predicted to understand better the fluid–structure interaction in the reflow oven. The considerations of air flow and thermal effects enhanced the study of fluid flow on the PCB assembly. Moreover, the Cu pillar technology challenges are also highlighted in this review. This review paper is expected to provide necessary information and direction to future researchers and industrial engineers when designing a brand-new surface-mounted component. [ABSTRACT FROM AUTHOR]

In this paper, a micro-bump tool is designed to prepare micro-bumps on the rake face of different tools for cutting titanium alloys. The study found that the micro-bump tool can effectively reduce the tool surface temperature (up to 26.83%) and reduce tool wear (up to 25.2%) due to the presence of bumps that change the contact state between the chip and the tool surface. The only downside is that the cutting force during cutting is higher than with ordinary tools. Aiming at this downside, this paper studies the cutting states (20–600 °C) of three conventional tools and corresponding micro-bump tools at different heat-assisted temperatures by using heat-assisted machining technology. The study found that the application of heat-assisted machining technology can effectively reduce the cutting force of the micro-bump tool, while retaining the advantages of the micro-bump tool, which can reduce temperature and reduce wear at different hot working temperatures. [ABSTRACT FROM AUTHOR]

The heat source based on the self-propagation reaction of Al/Ni thin foil has the characteristics of concentrated heat, fast temperature rise/fall rate and small heat-affected zone; it can complete the melting and solidification crystallization of solder within milliseconds to realize solder interconnection, which can solve the problems of damage to heat-sensitive materials and components caused by monolithic heating of package structure. However, due to the highly non-stationary interconnection process, the resulting microstructure morphology may affect the service performance of the interconnected joints. In view of this, to investigate the post-solder microstructure of solder based on the self-propagation reaction, this paper analyzes the effect of the initial microstructure on the post-solder microstructure by heating 300-μm-thick SnBi solder with a 40-μm Al/Ni thin foil. The results indicated that the short melting time could resulted in the incomplete melting of heterogeneous phases and the non-uniform distribution of elements during the melting process, which had a significant effect on the morphology and composition distribution of the solidified microstructure, as well as the hardness distribution of the melted zone. The above conclusions have the potential to improve the interconnection process based on the self-propagation reaction, which is critical for both theoretical guidance and engineering application. [ABSTRACT FROM AUTHOR]

In this paper a three-dimensional model of a novel electronic package has been developed using Finite element analysis to evaluate the shear load, tensile, bending and thermal stresses. Simulations of a complete flexible flip chip electronic packaging method are performed to minimize stresses on the packaged electronic device to improve robustness and reliability. Three component under-fill adhesives (Loctite 4860, Loctite 480 and Loctite 4902) and three circuit substrate materials (Kapton, Mylar and PEEK) are compared and the optimal thickness of each is found by shear load, tensile load, bending test and thermal expansion simulations. A fixed die size of 3.5 mm × 8 mm × 0.53 mm has been simulated and evaluated experimentally under shear and bending load. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. The Kapton substrate together with the Loctite 4902 adhesive were identified as the optimum in the simulation. The simulation of under-fill adhesive and substrate thickness identified an optimum configuration of a 0.045–0.052 mm thick substrate layer and a 0.042–0.045 mm thickness of the Loctite 4902 adhesive. The bending simulation has also been used to determine the neutral axis of the encapsulated electronic package in this paper, thus identifying the optimal material and thickness for the encapsulation layer of the package. [ABSTRACT FROM AUTHOR]

In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation. [ABSTRACT FROM AUTHOR]

Solder joints of Au-20wt%Sn (Au-20Sn) between real light-emitting diode Si chips and AlN substrates were fabricated using thermo-compression (TC) bonding. We investigated the microstructure of TC-bonded solder joints using scanning electron microscopy, transmission electron microscopy (TEM), and scanning transmission electron microscopy (STEM) and its effect on shear strength. The metallization system for the Au-20Sn solder consisted of Pt/Ti thin films on Si chips and an electroless Ni/Pd/Au layer on AlN substrates. The TC bonding was carried out at 280, 290, 300, and 310 °C for 0.2, 0.6, and 1.2 s. Samples were aged at 200 °C for up to 1000 h in a conventional oven. The performance of the solder joints was sensitive to joining temperature. When the solder joint was formed at a relatively low temperature, shear strength was low due to the unbonded regions in the solder joints. The shear strength increased with joining temperature and time. When the solder joints were formed at a relatively high temperature, shear strength was high. The solder joints were composed of δ-phase at both interfaces and ζ'-phase at the center. After aging at 200 °C for up to 1000 h, shear strength slightly decreased. The main fracture modes before and after aging were Si cohesive fracture and interfacial fracture between Si and Ti, respectively. TEM and STEM clearly indicated that the Pt layer remained at the solder interface after aging. The high shear strength was attributed to the strong interface between Pt and the Au-20Sn solder. [ABSTRACT FROM AUTHOR]

Lately, as electronic devices are continually becoming smaller, thinner, and multifunctional, there has been a growing demand for highly integrated packaging technologies. Accordingly, the application of flip-chip bonding technology has significantly increased to meet these demands. Therefore, the reliability evaluation of the micro-sized solder bumps used in flip-chip bonding and an understanding of the relevant mechanical properties has become essential. To evaluate the properties and reliability of Sn–2.3Ag (in wt%) flip-chip bump in various environments, this study compared the results of shear tests performed under three varying conditions, viz., shear heights (10, 15, 20, and 25 μm), shear rates (50, 100, 150, 200, 300, and 500 μm/s), and shear temperatures (25, 50, 100, 125, and 150 °C). A global bond tester was used for the shear tests and scanning electron microscopy was used to observe and analyze the fracture surfaces and joint cross sections subsequent to the tests. The experimental analysis showed that the shear test conditions had a significant impact on the shear strength and joint mechanical properties of the flip-chip bumps. The shear strength tends to decrease as the shear height and temperature increase, whereas it tends to increase in correspondence with increase in the shear rate. The correlations between the results of the mechanical characterization according to these test conditions were comparatively analyzed. [ABSTRACT FROM AUTHOR]

This paper investigates the influence of the welding process on the microstructure and mechanical properties of Au/Sn–3.0Ag–0.5Cu/Cu solder joints. In this study, the flip-chip LED chip and the substrate were connected by a heating platform, hot air reflow, and vacuum reflow soldering methods to form Au/Sn–Ag–Cu/Cu composite solder joints. Sn–3.0Ag–0.5Cu is selected as the solder. The microstructure of the solder joint interface and the inferred surface is studied to characterize the influence of different welding methods on the intermetallic compound (IMC) interface. The void ratio of the flip-chip solder layer was tested to characterize the effect of the effective connection area between the chip and the solder joint on the shear strength. The experimental results show that the void ratio of the solder joints welded by the heating platform is as high as 26%, the IMC interface thickness is higher, and the diffusion coefficient of the solder is the lowest. The void distribution of hot air reflow soldering joints is relatively uniform, and there is less solder residue on the fractured surface. Vacuum reflow soldering has the lowest void rate in the solder joints, and the solder joints have flat cross sections with almost no solder residues. The fracture occurs at the lower layer of solder. Considering comprehensively, when the soldering method is vacuum reflow, the IMC layer of the flip-chip solder joint is the thinnest, and the diffusion coefficient of the solder is the highest. There are almost no voids in the solder layer, and the mechanical properties of the solder joint are the best. At this time, the photo-thermoelectric parameters of the filament are the best, and the performance is the most stable and reliable. [ABSTRACT FROM AUTHOR]

Lead-free solders are commonly used in microelectronic packages in chip and board level interconnections. They primarily interact with other metals such as gold (Au), which is present in the under-bump metallization or surface finish on the chip and substrate, respectively, and with polymers, which are present surrounding the solders as underfills at the chip level and polymer collars or partial underfills at the board level. The interaction of solders with these materials at high temperatures (210–250 °C) has been widely studied and understood. However, the interaction of solders with these polymers and with Au at lower temperatures (100–120 °C), along with their diffusion behavior with these materials is not widely studied. In this research, the diffusion kinetics and mechanism of two solders, Sn57.6Bi0.4Ag (SBA), and Sn3Ag0.5Cu (SAC305), with melting points of 138 and 217 °C respectively, on bare Au, and in the presence of polymer films on Au was studied. On bare Au surface at 100 and 120 °C, diffusion rate dependence of (time)0.2 was observed for SBA solder, while a linear dependence on time was observed for SAC305 solder. In the presence of polymer films on Au, solder diffusion was observed at the interface of Au and polymer, as opposed to diffusion through the bulk polymer. In the presence of polymer films, a parabolic dependence of solder diffusion on time was observed for SBA, while linear dependence on time was observed for SAC305 solder, indicating that the presence of polymer affects the solder diffusion rate based on the difference between the melting temperature of the solder and the operating/test temperature. Furthermore, it was also observed that solder diffusion rate is inversely proportional to the polymer Tg. This study provides a better understanding for designing polymers for their use in chip and board level interconnections in microelectronics packages. [ABSTRACT FROM AUTHOR]

High entropy alloy (HEA) receives noticeable attention in the electronic industry, and one of the best ways to incorporate HEA with the existing assembly setup is to reinforce HEA particles in Pb-free solder. This paper investigates the properties of Sn3.5Ag0.5Cu (SAC 305) solder reinforced with HEA particles. FeCoCrNiCu particle was synthesized via ball milling and dispersed in SAC 305 paste by powder mixing technique. DSC analysis confirms a reduction in melting temperature and undercooling with the addition of HEA. The dispersion of HEA in the solder resulted in a significant refinement in β-Sn grain size, Ag3Sn, and Cu6Sn5 IMC particle size. Also, SAC 305 with 0.2 wt% HEA noted a better spreading performance and lowest contact angle. 1608 chip capacitor/HEA reinforced solder joint was assembled, subjected to − 40 to + 125 °C thermal shock, and tested for the shear strength. The reliability analyzed through Weibull analysis showed a 30% increase in the 75% survival probability strength for HEA-added joints. Also, HEA addition till 0.1 wt% suppressed the growth of (Cu, Ni)6Sn5 IMC after thermal shock cycles. After 1000 thermal shock cycles, 0.1 wt% HEA-added solder retained the shear strength of 22.5 MPa, equivalent to the strength exhibited by the SAC 305 in the as-reflow condition. [ABSTRACT FROM AUTHOR]

In order to control the interfacial intermetallics of the commonly used soldering joint in the electronics packaging products, copper and nickel-plated copper were selected as the substrates, SAC305 was selected as the solder, and a series of experiments were conducted. The pure copper was plated with nickel and then the nickel-plated copper substrate was heat-treated before reflow soldering. Effects of substrate heat treatment on reflow soldering and aging of the soldered joints were studied. The results show that the heat treatment of nickel-plated copper substrate before reflow soldering can enhance the adhesion between the substrate and the plated coating and it can inhibit the growth of interfacial intermetallic compound (IMC). In the aging process, the IMC layer thickness of the soldered joint without heat treatment on the substrate before reflow is thicker than that of the soldered joint with heat treatment before reflow. The IMC growth rate of the interfacial layer of the soldered joint without heat treatment on the substrate before reflow is 5.854 × 10–17 m2 s−1; the IMC growth rate of the interfacial layer of the soldered joint with the substrate heat-treated before reflow soldering is 3.193 × 10–17 m2 s−1. In the shear test, the shear strength of the solder joints with heat treatment on the substrate before reflow soldering is higher than that of the solder joints without heat treatment before reflow soldering. [ABSTRACT FROM AUTHOR]

Crystal growth of eco-friendly, ultrawide bandgap aluminium gallium nitride (AlGaN) semiconductor-based ultraviolet-B (UVB) light-emitting diodes (LEDs) hold the potential to replace toxic mercury-based ultraviolet lamps. One of the major drawbacks in the utilisation of AlGaN-based UVB LEDs is their low efficiency of about 6.5%. The study investigates the influence of Al-graded p-type multi-quantum-barrier electron-blocking-layer (Al-grad p-MQB EBL) and Al-graded p-AlGaN hole source layer (HSL) on the generation and injection of 3D holes in the active region. Using the new UVB LED design, a significant improvement in the experimental efficiency and light output power of about 8.2% and 36 mW is noticed. This is accomplished by the transparent nature of Al-graded Mg-doped p-AlGaN HSL for 3D holes generation and p-MQB EBL structure for holes transport toward multi-quantum-wells via intra-band tunnelling. Based on both the numerical and experimental studies, the influence of sub-nanometre scale Ni film deposited underneath the 200 nm-thick Al-film p-electrode on the optical reflectance in UVB LED is investigated. A remarkable improvement in the efficiency of up to 9.6% and light output power of 40 mW, even in the absence of standard package, flip-chip, and resin-like lenses, is achieved on bare-wafer under continuous-wave operation at room temperature. The enhanced performance is attributed to the use of Al-graded p-MQB EBL coupled with softly polarised p-AlGaN HSL and the highly reflective 0.4 nm-thick Ni and 200 nm-thick Al p-electrode in the UVB LED. This research study provides a new avenue to improve the performance of high-power p-AlGaN-based UVB LEDs and other optoelectronic devices in III–V semiconductors. [ABSTRACT FROM AUTHOR]

A technique and technology for manufacturing both LED chips and packaged LEDs from AlInGaN/GaN heterostructures grown on novel SiC/Si substrates synthesized by the method of matched substitution of atoms is described. We have studied the current-voltage characteristics, electroluminescence spectra, and dependence of output power and external quantum efficiency on the current. It is shown that the presence of pores in the SiC/Si substrate, which are naturally formed during its growth, leads to a significant increase in the quantum efficiency of LEDs compared with the quantum efficiency of LEDs fabricated on silicon without a SiC sublayer. [ABSTRACT FROM AUTHOR]

Based on the fact that flip chip without front-side bonding wire, a correlated color temperature (CCT) tunable chip on board (COB) light emittin g diodes (LED) light source was fabricated, by screen printing technology before the phosphor was coated on the whole luminous surface. A part of the blue LED chips in the light source excites the fluorescent glue to produce a warm white light (CCT = 2631 K), and the other part produces cool white light (CCT = 6181 K). When changing the driving current ratio of the two parts of the chips, the CCT of COB LED light source can be continuously adjusted between warm and cool white light. According to the measured data, the relationship between the CCT and the current ratio of the two parts is obtained by fitting. Within the tunable range of the CCT (2631 K to 6181 K), the color rendering index (CRI) is about 90. The minimum is 89.3 and the maximum is 93.1. While achieving tunable CCT and high CRI, the LED light source has a luminous flux of 1938.76 lm on a circular surface with a diameter of 11 mm. The overall luminous efficiency is close to 100 lm/W. [ABSTRACT FROM AUTHOR]

Electronic devices need to work at high temperature in some fields for a long time, peculiarly step soldering technology, primary packaging and flip–chip connections, etc., along with the application of electronic products more and more widely. These phenomena promote the further development of high-temperature solders. Because of the high melting temperatures of Sn-Ag and Sn-Sb, they are suitable for high-temperature fields such as automotive electronics and avionics. In this review, the influences of trace elements and nanoparticles on microstructure, intermetallic components (IMC) growth, mechanical properties, wettability, melting behavior, and creep behavior of Sn-Ag and Sn-Sb solders have been summarized systematically. It was found that the addition of trace elements or nanoparticles into solders to be beneficial in improving the performance of Sn-Ag and Sn-Sb solders. Besides, the melting behavior of the solder at high temperatures can be further improved if Sn-Ag and Sn-Sb are used better as high-temperature solders. [ABSTRACT FROM AUTHOR]

In this work, we study the Transient Liquid Phase Bonding (TLPB) for flip chip interconnexion using copper pillar and SnAg solder alloy technologies. Cu and SnAg bumps with a size of 90 × 90 µm2 were deposited using electroplating process with a thickness of 20 µm and 15–30 µm, respectively. Two types of Cu were deposited: with or without additives. Before the TLPB process, soldering experiments with or without pre-reflow were carried out at 250 °C in order to insure a good filling of the joint. Afterwards, isothermal holdings up to 4 h were performed in the temperature range between 250 and 350 °C under air atmosphere. Two main aspects of Cu/SnAg system are studied and analyzed: (i) the evolution of morphology, microstructure, and growth kinetics of intermetallics (IMCs) during the TLPB and especially (ii) the formation and growth of gas bubbles within the liquid solder during TLPB process. Destructive (scanning electron microscopy) and non-destructive (X-ray) characterizations are performed to analyze and understand the evolution of microstructure as well as the formation and evolution of cavities within the joint during the TLPB process. Non-destructive X-ray radiography with 5 µm resolution and 3D X-ray tomography analysis with 0.7 µm resolution were conducted for the same joint at different steps of its evolution between its initial state (just after the soldering process: about 3 min at 250 °C) and 4 h at 250 °C in order to follow "in situ" the evolution of volume defects inside the joint and especially the evolution of gas bubbles within the joints. [ABSTRACT FROM AUTHOR]

The low-k/ultra-low-k (LK/ULK) dielectric materials are incorporated in the 40 nm technology node and beyond to reduce resistance and capacitance (RC) delays and improve chip performances. However, the LK/ULK integrity becomes critical in a flip-chip process because of the LK/ULK materials' higher porosity and fragility in mechanics. In this paper, we proposed a three-dimensional (3D) one-level global/local finite element model to study stresses and fracture behaviors in the chip with ULK dielectrics in the heating flip-chip process using SIMULIA ABAQUS software. The global model includes an effective thin layer that is equivalent to Cu/low-k multilayer interconnections. On the basis of stress analysis, the precracks at different locations of back-end of line (BEOL) were introduced to estimate the values of energy release rate (ERR) along the 3D crack fronts and the possible crack extension was discussed. Furthermore, the ERR affected by the ULK modulus, polyimide thickness and copper pillar diameter was investigated. The analysis reveals that the values of ERR are higher in upper layers of the BEOL and their values at interfaces of Cu/ULK are as much as two times than in ULK. The ERR reaches its maximum value under the edge of copper pillar with higher first principal stresses. The crack propagation becomes critical due to a quickly rising value of ERR when the polyimide (PI) thickness or the diameter of copper pillar is decreased. The study helps to understand the fracture behaviors in BEOL of an advanced chip during a packaging process. [ABSTRACT FROM AUTHOR]

The effect of Ni on the gold embrittlement in the Sn/Au/Ni solder bump was studied in this paper. The mechanical properties of (Au1−x,Nix)Sn4 (x = 0, 0.25, 0.5) bulk, β-Sn/(Au1−x,Nix)Sn4 interface and Ni3Sn4/(Au1−x,Nix)Sn4 interface were calculated based on first principles, respectively. For bulk (Au1−x,Nix)Sn4, the ratio between bulk modulus and shear modulus shows that the addition of Ni into bulk AuSn4 would increase the brittleness, which could lead to bulk gold embrittlement. For the (100) β-Sn/(080) (Au1−x,Nix)Sn4 interface, the introduction of Ni into AuSn4 would increase the adhesion energy of interface, indicating strengthening the interface. While for (111) Ni3Sn4/(080) (Au1−x,Nix)Sn4 interface, the inclusion of Ni into AuSn4 would decrease the adhesion energy and deteriorate the bonding strength of interface. Furthermore, the cracks are prone to initiate at the (111) Ni3Sn4/(080) (Au1−x,Nix)Sn4 interface in the ideal tensile simulation, indicating that the introduction of Ni into AuSn4 would cause the interfacial gold embrittlement, which is usually not concerned in previous theoretical studies. [ABSTRACT FROM AUTHOR]

The present work investigated the effect of Ag additives on the consumption of cathode Cu pad under electromigration in a current-stressed Cu/Sn3.5Ag/Cu flip-chip structure. The consumption rate of a cathode Cu pad in a pure Sn system is faster than that of a cathode Cu pad in a Sn3.5Ag system at 80℃ by a factor of 10. Using the kinetics of the consumption equation, the activation energy in the consumption of a cathode Cu pad was calculated. The activation energy (0.65 eV) of the consumption of a cathode Cu pad in a Cu/Sn3.5Ag/Cu flip-chip structure under electromigration (EM) is slightly greater than that (0.62 eV) of the consumption of a cathode Cu pad in a Cu/Sn/Cu flip-chip structure under EM. The dissolution of Cu flux is discussed, and the possible effect of Ag additives on the consumption rate of a cathode Cu pad under EM is proposed. The Ag additives reduced the deficiency of Cu solubility in a solder matrix near the cathode Cu/solder interface, which is the main factor in the reduction of Cu pad consumption. Moreover, the Ag3Sn phase forming on the cathode Cu6Sn5 interface protects Cu6Sn5 from dissolving into the Sn3.5Ag solder matrix under EM. [ABSTRACT FROM AUTHOR]

We report a simple and low-cost at room temperature and atmospheric pressure synthetic method for highly stable and photoluminescence (PL) Mn2+-doped CsPb(Br/Cl)3 nanocrystal (NCs) thin films with high Mn-to-Pb feed ratio. The XRD, EDS, and XPS results confirm that Mn ions can be significantly doped in host CsPb(Br/Cl)3 NCs. PL spectra show multi-color luminescence, which is related to host exciton and Mn2+ dopant state emission, respectively. In addition, the optical properties of Mn2+-doped NCs present the good thermal stability even after 35 days. Furthermore, light-emitting diodes were constructed by employing as-prepared Mn2+-doped NCs (Mn-to-Pb feed ratio of 5:1) and CsPbBr3 with the commercial UV chip, demonstrating that Mn2+-doped NCs are applicable to the color converters for the potential field of lighting and display. [ABSTRACT FROM AUTHOR]

Nano/micron-silver paste has been applied in high-temperature packaging of chips as a potential lead-free solder. At specific sintering temperature, the particle size in the silver paste affects the sintering quality, which plays an important role in the mechanical properties of the sintered nano/micron-silver materials. In the current study, the macro- and micromechanical properties of the sintered specimens by three micron-silver paste with different average particle sizes were studied. It was found that the tensile and shear strength of the micron-silver joint sintering at 300 °C for 50 min decreased gradually with the increase in average particle size, while the compressive strength and fracture strain increased with the increase in average particle size. Scanning electron microscope analysis showed that smaller silver particle size leads to better sintered effect. At the microlevel, the creep properties of specimens sintered with three kinds of micron-silver paste were studied by nanoindentation experiment. Based on the entropy theory and continuous damage mechanics, a micro-creep model incorporating damage was developed. The proposed model could accurately predict the micro-creep compared with the nanoindentation experimental results. [ABSTRACT FROM AUTHOR]

The metallic bump-assisted resistance spot welding (MBaRSW) weld formed between Al and steel had higher strength and better ductility than the RSW welds. The fracture behavior was investigated for both the RSW weld and MBaRSW/Al weld by printing metallic bumps on an Al sheet prior to welding. The results showed that a larger nugget size, thinner intermetallic compounds (IMC) layer and smaller thinning of the base metal (BM) yielded MBaRSW/Al welds with better properties. With increasing welding current, the nugget size, thickness of the IMC layer and thinning of the BM all increased, causing the weld strength to first increase and then decrease. During lap-shear tests, all RSW welds fractured by the interfacial failure (IF) mode and exhibited poor properties, resulting from its thick IMC layer, interfacial defects and large thinning of the BM. The MBaRSW/Al welds failed by the IF mode, mixed failure (MF) mode and partial button pull-out failure (PBF) mode with the increasing welding currents. As a result, the nugget size and the thickness of the IMC layer determined the MBaRSW/Al weld property and failure mode, and the thinning of the Al sheet had a large effect on the properties and failure mode of the MBaRSW/Al welds at high welding currents, e.g., 11 kA. [ABSTRACT FROM AUTHOR]

In the actual production process, soldering is a key step in the flip-chip packaging process. The reliability of the interconnection interface of flip-chip LED chips is considered to be one of the most important reliability issues. This paper studies the influence of different soldering temperatures on the microstructure and shear behavior of the Au/Sn-3.0Ag-0.5Cu/Cu solder joints of flip-chip LED chips. The lead-free solder Sn-3.0Ag-0.5Cu was selected as the solder. The microstructure of the intermetallic compound (IMC) interface and the inferred surface of the solder joint is observed, and the microstructure evolution of the solder joint is analyzed. The void ratio of the solder joints at 250°C, 260°C, 270°C, 280°C, and 290°C soldering temperature was tested to characterize the influence of the contact area between the chip and the solder joint on the shear stress. In addition, the solder joints were aged for 1000 hours in an environment with a relative humidity of 85°C/85%, and a shear test was performed to evaluate the influence of the interface reaction on the mechanical reliability of the solder joints during the isothermal aging process. The research show that when the soldering temperature is 270°C, the Au on the bottom of the chip, and the solder and Cu on the substrate have fully reacted, and the solder joints have high shear resistance. The shear strength of the aging solder joints increases first and then decreases, because the high temperature repairs the defects in the solder layer caused by the low soldering temperature to a certain extent. With the extension of aging, cracks and voids gradually appear at the fracture interface, and the effective contact area decreases. The shear strength of the solder joint decreases, and the fracture mode becomes brittle. [ABSTRACT FROM AUTHOR]