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It seems impossible to use silicon oxide as a suitable gate dielectric material in metal-oxide-semiconductor field effect transistors. Many researchers have studied various metal oxides, nitrides, composite, and hybrid materials in search of dielectric materials that can replace silicon oxide. Each of these materials has advantages and disadvantages. In the present work, water-induced Lithium oxide (LiOx) with the organic PEIE (polyethylene imine ethoxylated) materials has been synthesized and studied. One advantage of the present work is using deionized water for getting (LiOx) precursor solution from lithium nitrate without the use of any toxic additives, resulting in a low cost-effective and eco-friendly synthesis. By fabricating three organic field effect transistors (OFETs) with LiOx/ PEIE nanocomposite materials with the same weight ratio (1:1), desirable electrical characteristics such as higher carrier mobility (μ) of 47.3 cm2V−1 S−1 , higher on-off current ratio (Ion/Ioff) of ∼105 , minima threshold voltage (Vth) shift of ∼ 0.6 (±0.2) V, lower subthreshold swing (SS) of 3.12 mV/decade and lower tunneling-, and leakage current density (J) of 2 (nA/cm2) could be found which demonstrated eco-friendly water-induced LiOx/ PEIE can be used as an alternative gate dielectric for the future of the OFET devices. [ABSTRACT FROM AUTHOR]

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices. Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length. [ABSTRACT FROM AUTHOR]

A c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO) possesses unique properties beneficial for thin-film transistors (TFTs). In this study, we investigate the effect of oxygen ratio and radio frequency (RF) power on the structural, electrical, and operational characteristics of CAAC-IGZO thin films. Films were deposited on SiO2 substrates using an RF sputtering system equipped with a target containing In, Ga, Zn, and O with a composition ratio of 1:1:1:4. The effect of oxygen percentage on the structural characteristics was analyzed by X-ray diffraction (XRD), transmission electron microscopy (TEM). The oxygen percentage in the film was found to play a crucial role in forming the CAAC-IGZO and orientation of the thin films. With increasing O2 fraction, the (009)-preferred orientation of the films improved. X-ray absorption spectroscopy also validated the improved orientations of the CAAC-IGZO with high O2 concentrations up to 70%. In terms of TFT performance, however, the device with 3.3% oxygen exhibited the best performance with a saturation mobility of 10.9 cm2 V− 1 s− 1. TFT devices were prepared at a low oxygen fraction (10%) with different RF power inputs from 100 to 250 W, where the device prepared with highest power (250 W) showed the best performance. [ABSTRACT FROM AUTHOR]

Indium-Yttrium codoped ZnO (ZnO:In-Y) thin films were prepared by sol–gel spin-coating technique on glass substrates at room temperature and annealed at 500°C for 1 h. The indium was incorporated with a constant concentration of 2 at% and yttrium was introduced with different concentrations of 1, 2 and 3 at%. X-ray diffraction patterns indicate that ZnO:In-Y thin films are polycrystalline with a hexagonal wurtzite structure. The preferred orientation is along the (002) plane perpendicular to the surface of the glass substrate. No additional diffraction peaks corresponding to secondary phases confirmed that the In and Y ions were uniformly distributed inside the samples. Transmittance analysis showed high transparency in the visible region with some extension to the near-ultraviolet region. Each thin film is composed of two different phases implying two different optical bandgaps; the amorphous phase manifests evidently higher optical bandgap, higher Urbach energy and lower refractive index in comparison with the crystalline phase. The amorphous phase is created under the effect of the amorphous glass substrate having an ultrawide bandgap. Transparency improvement in the near ultraviolet region depends on the amorphous phase rate. The resistivity measurements revealed that the lowest electrical resistivity value was 4.49 × 10–3 Ω. cm obtained for ZnO:In (2 at%)-Y (1 at%) thin film. These ZnO:In-Y thin films can have a big interest in the solar cell industry; can be used to fabricate thin film transistors and ultraviolet light-emitting diodes. [ABSTRACT FROM AUTHOR]

This study presents a method for growing and characterizing isolated and coalesced ZnO nanorods on a SiO2/p-Si substrate using the chemical bath deposition (CBD) technique. Characterizations of the nanorods were investigated using an X-ray diffractometer (XRD), atomic force microscopy (AFM), photoluminescence spectrofluorometer, and I–V parameter analyzer. The growth of ZnO nanorods significantly impacts the coalesced surface morphology and quantitative structural parameters. Potentiality of the ZnO nanorods based thin film transistor (TFT) as NH3 gas sensor has been explored. Experimental findings of the fabricated device structure were found to be well in agreement with the similar prototype structure simulated in TCAD environment. Maximum drain currents deviation between simulation and experimental study were found to be negligibly ± 0.2%. The ZnO nanorods-based TFT exhibits excellent room temperature sensitivity of ~ 226% at 50 ppm NH3 with threshold voltage shift towards lower VGS (from 9 V in air to 6 V in 50 ppm NH3). The fast response (14 s) and recovery (4 s) characteristics of the TFT sensor proved to be potentiality towards ammonia leakage detection and making it highly useful for industrial safety applications. The room temperature nanorods ammonia sensing mechanism were correlated through band bending at the grain boundaries interfaces following neck-controlled depletion model. [ABSTRACT FROM AUTHOR]

In this paper a Hetero-Dielectric Macaroni Channel Cylindrical Gate All Around FET (HD-MC CGAA FET) is proposed for reduced gate leakage analog application. The proffered device is also compared with a conventional Nanowire FET (NW-FET) and Dual Metal Hetero-Dielectric Cylindrical Gate All Around FET (DM-HD CGAA FET) so as to indicate the device efficiency of HD-MC CGAA FET. Both DM-HD CGAA FET and HD-MC CGAA FET have a combined vacuum dielectric at the drain with a silicon dioxide (SiO2) gate dielectric at the source. The structure has a symmetric gate oxide that is excellent for low power applications because of its considerably lower BTBT and OFF state gate leakages. GIDL of the HD-MC CGAA FET is lower, suggesting that this device has better insulation against leakages and its ION/IOFF ratio is higher making it better for digital applications. Based on the qualitatively obtained results, ION/IOFF ratio of HD-MC CGAA FET is 856 times better than NW-FET and 309 times better than DM-HD CGAA FET. GIDL current of HD-MC CGAA FET is measured to be 10–14 A as compared to 10–12 A of DM-HD CGAA FET and 10–10 A of NW-FET. It has also been entrenched that HD-MC CGAA FET has more promising IDS, gm, gd, GIDL, hole concentration, Transconduction Generation Factor and ION/IOFF ratio than the existing NW-FET and DM-HD CGAA FET making it highly applicable for low leakage and high frequency digital and analog application. [ABSTRACT FROM AUTHOR]

In this study, organic field-effect transistors (OFETs) were fabricated using plasticized poly(methyl methacrylate) (PMMA) as the gate dielectric and copper phthalocyanine (CuPc) as the active layer. Propylene carbonate (PC) was used as a plasticizer material. The dielectric properties of the plasticized PMMA were investigated in detail and the OFET parameters were examined. The effective capacitance (Ci) of plasticized PMMA was measured as ~ 500 nF cm−2 (at 100 Hz), which is almost 70 times higher than that of pure PMMA. This increase in effective capacitance led to significant improvements in various key parameters of the fabricated OFETs. High hole field-effect mobility values (0.81 cm2 V−1 s−1), low threshold voltages (~ ±0.1 V), and low operating voltages (0 to ±0.8 V) were achieved by using the plasticized PMMA dielectric. The temperature dependence of the fabricated OFETs was also investigated, and the activation energy of CuPc was estimated as 29.3 meV. The plasticized OFETs demonstrated excellent stability over 3600 measurement cycles carried out in an ambient atmosphere. This demonstrated stability of the fabricated OFETs reinforces the practical feasibility of this material combination strategy, positioning it as a key advancement in the field of solution-processable gate dielectrics. [ABSTRACT FROM AUTHOR]

FinFETs ensured the continuation of semiconductor industry with reliable, high performance and low power devices fabricated at sub-100 nm technology nodes. These FinFETs are able to suppress the Short Channel Effects quite effectively while decreasing the leakage currents. Below 22 nm gate lengths, the SCEs resurfaced. To suppress these effects, the thickness of the gate oxide reduced. As the gate oxide thickness reached below 2 nm, the leakage currents started increasing again. Thus arose the need for replacing SiO2 with high permittivity dielectric materials like Zirconium Dioxide, Hafnium Oxide, Aluminum Oxide and Silicon Nitrate. Research also suggested the use of Multi Fin architectures to enhance the drain currents. The focus of this paper is to develop multiple fin 08 nm gate length SOI FinFETs having three fin architecture where the gate oxide of each fin consists of a stacked combination of 0.5 nm of high-k dielectrics atop another layer of 0.5 nm of SiO2 to reduce the leakage currents and other SCEs. The use of 3-Fin structures significantly enhances the drain current leading to higher switching speeds for faster CMOS fabrication and optimized device performance towards semiconductor industry. [ABSTRACT FROM AUTHOR]

This article reports the effects of incomplete ionization on the low power performance of silicon-on-insulator (SOI) n-p-n dual-gate tunnel field-effect transistors (TFET) through calibrated technology computer-aided design simulations. The effects of drain-induced barrier thinning and resistivity profiles are reported for the proposed device in the presence and absence of incomplete ionization. A current sensitivity parameter is considered for analysis, which refers to the deviation of the drain current of the device with incomplete ionization included from the case without incomplete ionization. Considering the Altermatt incomplete ionization parameters for boron and arsenic dopants in the device of interest, this article presents the investigation of incomplete ionization for various gate work functions, and mobility models (doping-dependent models: Masetti, Arora, and Philips Unified, and mobility degradation models: University of Bologna, Lombardi, and Inversion and Accumulation Layer). The impact of a trap-assisted tunneling model on sensitivity is also reported. [ABSTRACT FROM AUTHOR]

A design and topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3 matrix. For the given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only is the complete suppression of the quantum barrier for electrons by a positive gate voltage ensured but also the minimum possible electrical resistance of the transistor channel is achieved. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the nonparabolic nature of the band structure of the semiconductor. [ABSTRACT FROM AUTHOR]

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications. [ABSTRACT FROM AUTHOR]

Top gate a-InGaZnO (IGZO) thin-film transistors (TFTs) annealed at high temperature show excellent initial current–voltage (I–V) characteristics. However, when they are exposed to positive gate bias for a long time, hump can occur in the subthreshold region. This abnormal hump is accelerated at a higher positive gate voltage and mitigate by a negative gate voltage. While the strength of the hump is irrelevant to a change in channel width, it relies significantly on channel length. This phenomenon might be due to mobile Na ions diffused from a glass substrate migrating toward the back and edge side of the IGZO semiconductor by a vertical gate electric field. When a layer of Al2O3 is formed between the IGZO semiconductor and the glass substrate, the hump phenomenon could be successfully solved by serving as a barrier for Na ions moving into the IGZO. [ABSTRACT FROM AUTHOR]

Reservoir computing can more efficiently be used to solve time-dependent tasks than conventional feedforward network owing to various advantages, such as easy training and low hardware overhead. Physical reservoirs that contain intrinsic nonlinear dynamic processes could serve as next-generation dynamic computing systems. High-efficiency reservoir systems require nonlinear and dynamic responses to distinguish time-series input data. Herein, an interface-type dynamic transistor gated by an Hf0.5Zr0.5O2 (HZO) film was introduced to perform reservoir computing. The channel conductance of Mott material La0.67Sr0.33MnO3 (LSMO) can effectively be modulated by taking advantage of the unique coupled property of the polarization process and oxygen migration in hafnium-based ferroelectrics. The large positive value of the oxygen vacancy formation energy and negative value of the oxygen affinity energy resulted in the spontaneous migration of accumulated oxygen ions in the HZO films to the channel, leading to the dynamic relaxation process. The modulation of the channel conductance was found to be closely related to the current state, identified as the origin of the nonlinear response. In the time series recognition and prediction tasks, the proposed reservoir system showed an extremely low decision-making error. This work provides a promising pathway for exploiting dynamic ion systems for high-performance neural network devices. Physical reservoirs that contain intrinsic nonlinear dynamic processes could serve as next-generation dynamic computing systems. Here, Liu et al. introduced an interface-type transistor based on oxygen ion dynamics to perform reservoir computing. [ABSTRACT FROM AUTHOR]

In this work, indium silicon oxide (ISO) thin-film transistors (TFT) were developed with molybdenum as the source and drain contact using sputtering and lithography techniques. The influence of channel length on the electrical properties of the ISO TFTs was studied by varying the channel length from ultra-short 5 µm to 100 µm. The highest mobility of 13.23 cm2/V s with an on/off ratio of 108 order was obtained for the ISO TFT post-annealed at 150°C with a channel length of 5 µm and width of 250 µm. In addition, the bias stress stability of the ISO TFT was measured. [ABSTRACT FROM AUTHOR]

Double-layered high-κ gate dielectric (high-κ NdHfO on low-κ SiO2) and p-Si gate electrodes with different doping concentrations are employed in the fabrication of InGaZnO thin-film transistors (IGZO TFTs) to investigate the effects of the low-κ SiO2 interlayer on the remote phonon scattering (RPS) of the high-κ gate dielectric and thus the carrier mobility in the IGZO channel. Compared with previous research on IGZO TFTs with single-layered NdHfO gate dielectric, the experimental results show that with the insertion of a SiO2 film between the NdHfO layer and the p-Si gate electrode, the carrier mobility performance presents obvious differences: (1) the mobility increment with increasing gate doping concentration falls around 56% due to the reduced gate screening effect on the RPS caused by the increased separation and thus weakened electrical coupling between the gate electrode and the high-κ NdHfO layer; (2) the disappearance of the large mobility reduction for the sample with gate doping concentration of 1.0 × 1018–1.9 × 1018/cm3 produced by the resonance between the gate electrode and the high-κ NdHfO layer (thus enhanced RPS) due to their weakened electrical coupling; and surprisingly, (3) the emergence of large mobility reductions for the two samples with gate doping concentrations of 2.8 × 1018–3.1 × 1018/cm3 and 2.7 × 1018–7.9 × 1018/cm3 caused by the resonance between the relatively rigid low-κ SiO2 interlayer and the adjacent gate electrode (thus enhanced RPS). In summary, this work demonstrates that the low-κ layer in a double-layered high-κ gate dielectric can also have significant effects on the RPS and thus carrier mobility in metal-oxide-semiconductor (MOS) devices. [ABSTRACT FROM AUTHOR]

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications. [ABSTRACT FROM AUTHOR]

In this paper, a new efficient technique is used in silicon-on-insulator metal–semiconductor field-effect transistors (SOI MESFETs) to simultaneously increase the breakdown voltage and drain current and also improve the frequency parameters. This proposed structure is presented for SOI MESFET with; he displaced gate contact toward the source region and creating distinct silicon oxide packets with different sizes under both sides of the gate electrode inside the channel. Gate electrode displacement from the middle of the device toward the source rises the transistor breakdown voltage. Increasing the distance between the drain and gate electrodes decrease the accumulation of equipotential lines in the corner of the gate on the drain side, and reduces the field, thereby increasing the breakdown voltage in the suggested device. In addition, moving the gate metal toward the source has negative effects on the frequency performance, so by adding two oxide zones on both sides of the gate region the device parasitic capacitances are suppressed to compensate the frequency performance. Numerical simulations reveal that the breakdown voltage in the basic and suggested structures are about 15 and 30 V, respectively. Also, the drain current of the presented structure shows a significant increase compared to its basic counterpart. Here, the maximum output power density is 0.32 W/mm for the presented device and 0.12 W/mm for the basic structure, indicating 166% enhancement. Also, the RF specifications of the suggested structure, including maximum available power gain, current gain, unilateral power gain, and maximum stable gain, were improved by 21, 66, 50, and 52%, respectively, and cutoff frequency in the basic structure is 19.5, increased to 21.5 GHz by applied adaptations. [ABSTRACT FROM AUTHOR]

In this manuscript, analog/RF performance, linearity, harmonic distortion, small signal AC performance and scattering parameter (S-parameters) metrics of gate-stack DM nanowire (NW) FET (4H-silicon carbide) have been critically examined with nanowire field effect transistor (NW FET) (silicon), nanowire (NW) field effect transistor (FET) (silicon carbide) and dual metal (DM) nanowire field effect transistor (NW FET) (silicon carbide). For a fair comparison, electrical characteristics like the majority and minority charge carrier concentration, energy and velocity in ON-State (Vgs = Vds = 1.0 V) and OFF-State (Vgs = 0.0 V and Vds = 1.0 V) have been evaluated. This paper combines the advantages of dielectric material having gate-stack HfO2 (Hafnium oxide) with high-k and Al2O3 (aluminium oxide) to attain a superior Ion/Ioff ratio, intrinsic gain (gm/gd), GFP (gain frequency product), GBWP (gain bandwidth product), TFP (transconductance frequency product), GTFP (gain transconductance frequency product), early voltage (Vea), maximum frequency of oscillation (fmax), gm2, gm3 (higher-order transconductances), UPG (unilateral power gain), maximum transducer power gain and delay. To check the relevancy of the device for RFIC applications, linearity assessment is performed by evaluating its several figure of merits like VIP2, voltage interception points (VIP3), third-order intercept point (IIP3), 1-dB compression point, third-order intermodulation distortion (IMD3), HD2, HD3, harmonic distortions (THD) for all contemplated devices. Additionally, scattering parameters have been examined to affirm the small signal performance. This is being deduced further that our proposed device analysis exhibits improved electrical and linearity characteristics, and all of these factors contribute to its use in high-power and high-frequency implementation. [ABSTRACT FROM AUTHOR]

A zinc oxide (ZnO)/silver double Schottky junction tunnel effect transistor was fabricated by radio frequency magnetron sputtering. ZnO was used as the active layer of the transistor, and the electrical characteristics of the specimen were analysed. Through the analysis and calculation of the transfer characteristics, transconductance, output resistance, voltage amplification coefficient, carrier mobility, and switching current ratio, the results show that the device has excellent high-current output. When the gate bias VGS = 0.2 V, VDS = 3 V, the drain-source current IDS = 8.0 × 10−3 A, reaching the milliamp level. The threshold voltage is only about 1.35 V, the switch current ratio of the device is 4.8 × 104, the ZnO thin film carrier mobility is 0.33 cm2V−1 s−1, the device has a small output resistance and large voltage amplification. Through the analysis of the output voltage-current characteristics of the device, the operating current of the transistor exhibits a tunneling effect. ZnO thin-film transistors with a vertical structure are capable of outputting large currents. [ABSTRACT FROM AUTHOR]

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz. The progress of high-performance oxide-based transistors is essential for seamlessly integrating monolithic 3-D circuits into the CMOS backend. The authors propose using atomic layer deposition for ZnO due to its compatibility with low-temperature backend integration. They also successfully integrated ZnO TFTs with HfO2 RRAM in a 1 kbit 1T1R array, showcasing RRAM switching capabilities. [ABSTRACT FROM AUTHOR]

Hybrid molecules based on C60 fullerene and strained polycyclic hydrocarbons have been synthesized for the first time using the Bingel–Hirsch reaction. Thin films based on the synthesized hybrid compounds have been obtained and their surface morphology has been studied. Organic field-effect transistors have been fabricated based on thin films of the С60 fullerene adducts bearing fragments of strained polycyclic hydrocarbons. Current-voltage characteristics of the transistors have been measured and the mobility of the charge carriers has been calculated. [ABSTRACT FROM AUTHOR]

Surface defects have a significant impact on the performance of light-emitting diodes (LEDs). To reduce surface defects, surface passivation using zinc oxide (ZnO) nanoparticles utilizing the wet chemical precipitation method is effective. An LED is produced using capped ZnO. The structural components of an ITO/PEDOT:PSS/F8BT/1.ZnO/TPBi/LiF/Al-based LED demonstrates that the interaction of zinc oxide (1.ZnO) and poly(9,9-dioctylfluorene-alt-benzothiadiazole) (F8BT) at the interface leads to luminescence under an electric field. The current–voltage curve clearly demonstrates rectifying properties in the device, with a threshold voltage of about 5 V. At normal temperature, the device emits electroluminescence (EL) at a wavelength of roughly 527 nm (green) when forward bias is applied. [ABSTRACT FROM AUTHOR]

Top gate a-InGaZnO (IGZO) thin-film transistors (TFTs) annealed at high temperature show excellent initial current–voltage (I–V) characteristics. However, when they are exposed to positive gate bias for a long time, hump can occur in the subthreshold region. This abnormal hump is accelerated at a higher positive gate voltage and mitigate by a negative gate voltage. While the strength of the hump is irrelevant to a change in channel width, it relies significantly on channel length. This phenomenon might be due to mobile Na ions diffused from a glass substrate migrating toward the back and edge side of the IGZO semiconductor by a vertical gate electric field. When a layer of Al2O3 is formed between the IGZO semiconductor and the glass substrate, the hump phenomenon could be successfully solved by serving as a barrier for Na ions moving into the IGZO. [ABSTRACT FROM AUTHOR]

This study aims to examine the influence of the co-doped semiconductor nanostructure (Al-Cu):ZnO on the electro-optical properties of the E7 coded pure nematic liquid crystal structures and minimize the threshold voltage of pure E7 liquid crystal. To determine the ideal concentration ratios of the materials for the minimum threshold voltage, we employed different machine learning algorithms. In this context, we first produced twelve composite structures through lab experimentation with different concentrations and created an experimental dataset for the machine learning algorithms. Next, the ideal concentration ratios were estimated using the AdaBoost algorithm, which has an R 2 of 96% on the experimental dataset. Finally, additional composite structures having the estimated concentration ratios were produced. The results show that, with the help of the employed machine learning algorithms, the threshold voltage of pure E7 liquid crystal was reduced by 19% via the (Al-Cu):ZnO doping. [ABSTRACT FROM AUTHOR]

The electrical and physical characteristics of a cylindrical silicon field-effect nanotransistor (FET) with a fully enclosed gate with Al2O3 and HfO2 gate oxide dielectrics are discussed. The numerical simulation results show that the use of high k dielectrics has a noticeable effect on all the main characteristics of the transistor compared to silicon oxide. It follows from the data obtained that, when scaling, the degree of degradation of the electrical and physical characteristics of the transistor is correlated with the level of k: it decreases with the growth of k. This is due to the fact that the decrease in the effect of the gate on the characteristics of the transistor structure, especially in the subthreshold region, is partially compensated by the use of dielectrics with a high k. [ABSTRACT FROM AUTHOR]

A bottom gate staggered 30 nm Zn(1−x)Sn(x)O (x = 0.14) (TZO)-based thin-film transistors (TFTs) were fabricated using DC magnetron reactive sputtering method. Highly transparent 120 nm dc sputtered ZrO2 was used as a gate dielectric. The oxygen flow rate was varied from 20 to 24% during channel layer (TZO) coating and its effect on structural, morphological, optical, chemical, and electrical parameters were systematically studied. A nano scale roughness was noticed by atomic force microscopy (AFM), and ultra-smooth nature in root mean square roughness (RMS) was observed with an increment in the oxygen flow ratio. The increase in the oxygen-related defects with increase in the oxygen flow ratio in channel layer was evident from X-ray photoelectron spectroscopy (XPS). The electrical characterization of gate dielectric was carried out for Al–ZrO2–Al structure. The high capacitance density ~ 121.9 nF/cm2 for 120 nm ZrO2 was obtained from the capacitance–voltage (C–V) measurement. The fabricated TFTs operated in n-channel depletion mode and indicated pinch-off region at lower source–drain voltages. In addition, the transfer characteristics of TFTs confirmed Ion/Ioff ratio of 105, with a field effect mobility of 23 cm2/V.s. This low temperature processed TFT unlocks the possibility of use in the next generation foldable display technology. [ABSTRACT FROM AUTHOR]

In the current study, p-type thin-film transistors (TFT) based on poly(3-hexylthiophene) (P3HT) and zinc oxide (ZnO) nanoparticles with channel length L = 2.5 m, 5 m, 10 m, and 20 m were developed and characterized using solution-processed P3HT. Without any surface preparation, spin coating was used to create P3HT:ZnO thin films as an active layer on a SiO2/Si substrate. In order to better understand the relationship between the electrical performance and the channel length, we investigated the effect of varied channel length on the electrical characteristics of these transistors at room temperature in the saturation regime. The fabricated devices showed significant variation in electrical parameters as a function of channel length, including the threshold voltage (Vth), density of trapped charges (Ntrap), subthreshold slope (SS), density of the interface trap (Dit), field-effect saturation mobility (µsat), and current ratio (Ion/Ioff). This paper discusses the Gaussian DOS distribution (GDOS) of the P3HT:ZnO TFTs for various channel layer lengths using an analytical model for organic TFTs (OTFTs) based on the variable-range hopping (VRH) theory. This model appropriately describes the GDOS. Finally, we used a generic drift model to reproduce the output characteristics of TFT-P3HT. The derived theoretical results exhibit excellent agreement with the experimental data. The value of the mobility in the P3HT transistors is lower than that of the P3HT:ZnO blend, confirming the advantage of introducing the ZnO nanoparticles. [ABSTRACT FROM AUTHOR]

In this study, indium–gallium–zinc–oxide (IGZO) synaptic transistors gated by solid biopolymer electrolytes (SBEs) were fabricated on glass substrates. Ammonium bromide (NH4Br) was first doped in SBE-based alginate as the gate dielectric to study the performances of synaptic transistors. With the NH4Br doping, a high electric-double-layer capacitance of ~ 6.4 μF cm−2 was obtained for the biopolymer electrolyte, which could be attributed to the incorporation of excess protons into the electrolyte from the complexation between alginate and NH4Br. Moreover, synaptic functions based on this IGZO transistor gated by NH4Br-doped alginate were successfully emulated, including excitatory post-synaptic current, paired-pulse facilitation and post-tetanic potentiation. The present results may provide a solution for the performance improvements of synaptic electronics. [ABSTRACT FROM AUTHOR]

We demonstrate in-plane gate transistors based on the molybdenum disulfide (MoS2)/graphene hetero-structure. The graphene works as channels while MoS2 functions as passivation layers. The weak hysteresis of the device suggests that the MoS2 layer can effectively passivate the graphene channel. The characteristics of devices with and without removal of MoS2 between electrodes and graphene are also compared. The device with direct electrode/graphene contact shows a reduced contact resistance, increased drain current, and enhanced field-effect mobility. The higher field-effect mobility than that obtained through Hall measurement indicates that more carriers are present in the channel, rendering it more conductive. [ABSTRACT FROM AUTHOR]

Silicon microring resonators (Si-MRRs) play essential roles in on-chip wavelength division multiplexing (WDM) systems due to their ultra-compact size and low energy consumption. However, the resonant wavelength of Si-MRRs is very sensitive to temperature fluctuations and fabrication process variation. Typically, each Si-MRR in the WDM system requires precise wavelength control by free carrier injection using PIN diodes or thermal heaters that consume high power. This work experimentally demonstrates gate-tuning on-chip WDM filters for the first time with large wavelength coverage for the entire channel spacing using a Si-MRR array driven by high mobility titanium-doped indium oxide (ITiO) gates. The integrated Si-MRRs achieve unprecedented wavelength tunability up to 589 pm/V, or VπL of 0.050 V cm with a high-quality factor of 5200. The on-chip WDM filters, which consist of four cascaded ITiO-driven Si-MRRs, can be continuously tuned across the 1543–1548 nm wavelength range by gate biases with near-zero power consumption. [ABSTRACT FROM AUTHOR]

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel and the narrow bandgap source. It shows an Ion of 392 μA/μm, an Ioff of 8.8 × 10−17 A/μm, an Ion/Ioff ratio of about 4.4 × 1012, and a minimum subthreshold slope of 9.3 mV/dec at Vd = 1 V. We also analyze the influence of the gate oxide and metal work functions on the transistor characteristics. A numerical device simulator, calibrated to the experimental data of a vertical InAs–Si gate all around TFET, is used to accurately predict different features of the device. Our simulations demonstrate that the proposed vertical TFET, as a fast-switching and very low power device, is a promising transistor for digital applications. [ABSTRACT FROM AUTHOR]

Optoelectronic synapses are devices that use electromagnetic radiation to mimic synaptic plasticity and its related functions. Such devices are considered key elements for the implementation of neuromorphic computing systems, that is, based on the functioning of the brain, with sensing, memory and learning properties. This work demonstrates an optoelectronic device with synaptic properties based on a thin-film transistor (TFT) configuration, with the semiconductor channel consisting by a zinc oxide (ZnO) film deposited by RF magnetron sputtering. The synaptic properties take advantage of the phenomenon of persistent photoconductivity presented by the ZnO film. The incidence of light in the channel increases the electrical current intensity measured between the drain and source electrodes (IDS)—for a given potential applied to the gate electrode (VGS). With this, the synaptic functions of sensing, short- and long-term memory, learning and relearning, and paired pulse facilitation, are verified in the ZnO TFT. The variations in IDS caused by lighting with ultraviolet (UV) radiation can reach up to 108 A, which demonstrates the high sensitivity of the device, a crucial aspect for its effectiveness in terms of recognizing and discriminating the light stimulus. [ABSTRACT FROM AUTHOR]

In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A single device with both gate terminals is biased independently during 2D simulation to understand fundamental two-input Boolean gates (OR, NAND, AND and NOR). The vital element in attaining various logic functions using double-gate vertical TFET is deploying a gate–source connection with an appropriate choice of silicon body thickness. The OR and NAND gates are realized using n-type and p-type HJ-VTFETs, respectively, by applying an independent voltage at both gates. While the AND and NOR gates are realized using n-type and p-type HJ-VTFETs, respectively, employing the gate–source overlap method. These implementations show that an exclusive feature of TFETs, such as ambipolar conduction with tunneling dependent on gate–source overlapping, can be realized for logic functions. With such a compact implementation with HJ-VTFET, the present work revealed some serious problems, such as a large subthreshold swing (SS), a small ON-state current ( I ON ), and high propagation delay ( τ D ). For AND functionality, in contrast to pure Si-based-VTFET (Si-VTFET), the HJ-VTFET raised I ON / I OFF via 3rd-order magnitude with around 67% improvement in SS. Further, an OR gate is realized with proposed HJ-VTFET and revealed less τ D around 0.012 nS, compared to the other gates realized using HJ-VTFET. [ABSTRACT FROM AUTHOR]

The continuously growing need for quality assurance and systems integration in plastics manufacturing, promoted by Industry 4.0 technologies as well as interest in sustainability and recycling, creates significant opportunities for advanced multivariate in-mold sensing. This work describes the design of a multivariate shrinkage sensor (MVSS) incorporating a spring-biased pin with a digital linear displacement transducer to measure in-mold shrinkage directly. The multivariate sensor also incorporates a piezoelectric ring for cavity pressure measurement and an infrared detector for melt and mold temperature acquisition. The combined use of the sensor signals allows real-time process monitoring and prediction of the molded part dimensional quality. A design of experiments (DOE) was used to validate the sensor functionality for an amorphous high-impact polystyrene (HIPS) and a semicrystalline polypropylene (PP). The results indicated that the root mean square error of the predicted thicknesses was 6.3 microns (i.e., 0.21%) for a regression model based on the DOE factor settings, 4.8 microns (i.e., 0.16%) based on traditional cavity pressure and temperature data, and 3.4 microns (i.e., 0.11%) based on just the available MVSS data. The modeled main effects highlight the different shrinkage behavior of HIPS and PP indicating the need for in-mold shrinkage data. [ABSTRACT FROM AUTHOR]

An advanced hetero-dielectric gate oxide nanowires tunnel field-effect transistor (HD NW TET) with the spacer on both sides of the gate is proposed and analyzed. The performance characteristics of the NW TET were designed using ATLAS TCAD in 5-nm technology. In the hetero-gate dielectric NW TET, we used a nanomaterial oxide of hafnium oxide (HfO2) on the source side and silicon dioxide (SiO2) on the drain side. The advanced NW TET is proposed by adding high-k dielectric materials as nanospacers on the source and drain sides. The performance variations, hafnium oxide (HfO2) and silicon dioxide (SiO2), were used as spacers as nanomaterial oxides. The device has increased ON current while decreasing ambipolar conduction, and has a significantly smaller subthreshold swing due to its nanodimensions and nanoparticles. Therefore, the proposed dielectric material NW-TET has improved analog parameters and drain current characteristics. Therefore, the 5-nm advanced NW TET device is suitable for ultra-low-power applications. [ABSTRACT FROM AUTHOR]

In this study, ZnO/V2O5 hybrid nanocomposites were fabricated for UV light/H2 gas dual sensing device. V2O5 were sputtered on hydrothermally grown ZnO nanorods (NRs) for various times, and multiple material characterizations were performed on the nanostructures. Results indicate that the increase of defects and lattice strain may enhance the UV light photo-sensing capability, while the wrapping of V2O5 on ZnO NRs may block the gas molecule transport and degrade the hydrogen gas sensitivity. Addition of V2O5 was distinct from the stuttering of WO3 and IGZO on ZnO NRs. ZnO/V2O5 NRs are promising for future compact light/gas modulation devices. [ABSTRACT FROM AUTHOR]

Analysis has been carried out to check and study the working of a novel pocketed version of TFET in comparison to a conventional TFET. We have proposed a germanium pocket TFET using a dual dielectric (HfO2 near the source side and SiO2 near the drain side) and a gate which uses two separate materials at source/drain side for enhancement of TFET characteristics. These features help us to improve the SS, ION and ION–IOFF ratio. Germanium having a low band-gap enhances the tunneling at the source/channel (S/C) junction, thereby increasing the on-current. Dual dielectric further helps to increase the electric field at the S/C junction, hence escalating the tunneling and thereby the drain current in the on state. Our aim is also to reduce the ambipolar current. This is achieved by using a drain metal and a 10 nm gate/drain underlap. The operating drain voltage of our device is 0.4 V while the gate voltage is varied from −0.6 to 0.6 V. Simulation study clearly indicates that we have designed a device with much better characteristics like improved on-current (increased by two orders), higher ON current (ION) to OFF current (IOFF) ratio (ION/IOFF), lower ambipolarity (suppressed by ~ 7 orders) and a sharper SS of 30 mV/dec. AC analysis has also been carried out to study and inspect the device behavior at high frequency parameters. [ABSTRACT FROM AUTHOR]

In this research, we present the production of series of bottom-gate/bottom-contact hybrid thin-film transistors by utilizing a blend of poly(3-hexylthiophene) (P3HT) and zinc oxide (ZnO) as active layers. ZnO nanoparticles are used as electron acceptors in hybrid organic–inorganic-based thin-film transistors as well as electron extraction materials. The nanoparticles of ZnO were produced by the sol–gel protocol. The P3HT:ZnO nanocomposite layers were deposited on silicon dioxide using the spin-coating method. The experimental study indicated that the hysteresis phenomenon of the components can be controlled by varying the amount of ZnO nanoparticles in P3HT:ZnO hybrid blend active layers. As a result, a major improvement of electron transport was observed with the increase of ZnO nanoparticles amount in the active layer, indicates that trapping was reduced in the P3HT:ZnO/SiO2 insulator interface. Furthermore, with increasing the ZnO nanoparticles concentration in the active layer, a critical improvement in the reduction of the trap density at the active layer/SiO2 interface was noticed even without using a dielectric surface treatment. Therefore, these results indicate that the incorporation of ZnO nanoparticles into the P3HT polymer has a crucial role in reducing the trap density in the active layer at the active layer/SiO2 insulator interface, thereby allowing the enhancement the transistor efficiency in terms of carrier mobility, on/off current ratio, threshold voltage, sub-threshold voltage, interface trapped, and density trapped carriers. The fabricated organic thin-film transistors, with significant hysteresis depended on ZnO nanoparticles in the active layer, prove a high possibility to use them for low-cost non-volatile memory thin-film transistors and sensing array applications. The best electrical performance was obtained with the OFET-PZ100 device. Finally, the output characteristics for this thin-film transistor was reproduced by using an analytic model, and good consistency between the different results has been illustrated. [ABSTRACT FROM AUTHOR]

Doping a typical topological insulator, Bi2Se3, with Ag impurity causes a semiconductor–metal (S-M) transition at 35 K. To deepen the understanding of this phenomenon, structural and transport properties of Ag-doped Bi2Se3 were studied. Single-crystal X-ray diffraction (SC-XRD) showed no structural transitions but slight shrinkage of the lattice, indicating no structural origin of the transition. To better understand electronic properties of Ag-doped Bi2Se3, extended analyses of Hall effect and electric-field effect were carried out. Hall effect measurements revealed that the reduction of resistance was accompanied by increases in not only carrier density but carrier mobility. The field-effect mobility is different for positive and negative gate voltages, indicating that the EF is located at around the bottom of the bulk conduction band (BCB) and that the carrier mobility in the bulk is larger than that at the bottom surface at all temperatures. The pinning of the EF at the BCB is found to be a key issue to induce the S-M transition, because the transition can be caused by depinning of the EF or the crossover between the bulk and the top surface transport. [ABSTRACT FROM AUTHOR]

Indium-doped ZnO nanoparticles were synthesized by co-precipitation method using zinc nitrate hexahydrate and Indium (III) nitrate hydrate as precursor. Co-precipitation of indium-doped ZnO with various indium dopant concentrations 0–5 wt.% were obtained by calcination process at 500 °C for 2 h. The effects of indium additive in ZnO host lattice on structural, optical and electrical properties have been investigated by X-ray diffraction (XRD), Scanning electron microscopy (FE-SEM), Energy Dispersive Spectroscopy (EDS), Diffuse Reflectance Spectroscopy (DRS) and four-point probe. XRD results reveal that all Indium-doped ZnO nanoparticles have a single phase hexagonal wurtzite structure. The position of the main diffraction peak of ZnO shifted slightly toward small angle with grain size from 210 to 430 nm. SEM images indicated that the dopant of indium affected the surface morphology of ZnO nanoparticles. The incorporation of indium ions up to 4–5 wt.% reveals that ZnO host matrix can be transformed into the rod-like structure. The element composition in weight percentage of Zn, O and In were presented using EDS element mapping analysis. The results confirmed that the incorporation of indium is doped into the ZnO host matrix with a quite uniform distribution. The optical properties were examined by DRS. The optical transmittance decreases when the indium dopant increases. The absorption band edges also moved toward the longer wavelength as increasing the indium additives. The results indicated that the incorporation of In3+ ions replaces Zn2+ ions in host ZnO led to an increase in the defects inside ZnO. The calculated bandgap indium-doped ZnO decreased from 3.01 to 2.86 eV when indium dopant increased from 0 to 5 wt.%. The sheet resistance of indium-doped ZnO was observed by four-point probe measurement in room temperature. The electrical transport results suggested that n-doped by incorporation of 3 wt.% significantly affected the good conducting formation of ZnO. [ABSTRACT FROM AUTHOR]

Fast-growing wood has disadvantages, such as loose surface structure, poor weather resistance, high moisture absorption, and poor dimensional stability, which severely limit its value and application. In this paper, Polydimethylsiloxane (PDMS) was used to treat the fast-growing poplar veneer to improve the microstructure of the wood surface and provide a smooth substrate for depositing ZnO film. Nano-ZnO/PDMS double-layer structure wood was prepared by magnetron sputtering, and its structure, microscopic morphology, surface elements, anti-photochromic properties, and hydrophobic properties were characterized and tested. The results showed that the nano-ZnO/PDMS modified fast-growing wood did not destroy the natural structure of the wood. When the sputtering time was 120 min, the characteristic diffraction peaks of ZnO(100), ZnO(002), and ZnO(101) appeared near 2θ of 31.8°, 34.4°, and 36.3°. The weight percentage of surface Zn elements reached 55.09%, and the total color difference value of the nano-ZnO/PDMS double-layer structure wood (120 min) was 3.85, which was 80.4% lower than that of poplar veneer, showing obvious resistance to light discoloration. The sputtered ZnO nanoparticles can effectively combine with the PDMS-treated wood to form a ZnO film with a certain degree of crystallinity. The surface water contact angle reached 146.2°, which is close to superhydrophobicity and can maintain good hydrophobicity for a long time. In conclusion, the preparation of nano-ZnO/PDMS double-layer structure wood by magnetron sputtering formed a nanoscale rough interface, which enhanced the hydrophobic properties and anti-photochromic properties of fast-growing wood. [ABSTRACT FROM AUTHOR]

In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8–50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment. [ABSTRACT FROM AUTHOR]

We present a study on characteristics of operating region-dependent weight updates in a synaptic thin-film transistor (Syn-TFT) with an amorphous In–Ga–Zn–O (IGZO) channel layer. For a synaptic behavior (e.g. a memory phenomenon) of the IGZO TFT, a defective oxide (e.g. SiO2) is intentionally used for a charge trapping due to programming pulses to the gate terminal. Based on this synaptic behavior, a conductance of the Syn-TFT is modulated depending on the programming pulses, thus weight updates. This weight update characteristics of the Syn-TFT is analyzed in terms of a dynamic ratio (drw) for two operating regions (i.e. the above-threshold and sub-threshold regimes). Here, the operating region is chosen depending on the level of the gate read-voltage relative to the threshold voltage of the Syn-TFT. To verify these, the static and pulsed characteristics of the fabricated Syn-TFT are monitored experimentally. As experimental results, it is found that the drw of the sub-threshold regime is larger compared to the above-threshold regime. In addition, the weight linearity in the sub-threshold regime is observed to be better compared to the above-threshold regime. Since it is expected that either the drw or weight linearity can affect performances (e.g. a classification accuracy) of an analog accelerator (AA) constructed with the Syn-TFTs, the AA simulation is performed to check this with a crossbar simulator. [ABSTRACT FROM AUTHOR]

We present a study on characteristics of operating region-dependent weight updates in a synaptic thin-film transistor (Syn-TFT) with an amorphous In–Ga–Zn–O (IGZO) channel layer. For a synaptic behavior (e.g. a memory phenomenon) of the IGZO TFT, a defective oxide (e.g. SiO2) is intentionally used for a charge trapping due to programming pulses to the gate terminal. Based on this synaptic behavior, a conductance of the Syn-TFT is modulated depending on the programming pulses, thus weight updates. This weight update characteristics of the Syn-TFT is analyzed in terms of a dynamic ratio (drw) for two operating regions (i.e. the above-threshold and sub-threshold regimes). Here, the operating region is chosen depending on the level of the gate read-voltage relative to the threshold voltage of the Syn-TFT. To verify these, the static and pulsed characteristics of the fabricated Syn-TFT are monitored experimentally. As experimental results, it is found that the drw of the sub-threshold regime is larger compared to the above-threshold regime. In addition, the weight linearity in the sub-threshold regime is observed to be better compared to the above-threshold regime. Since it is expected that either the drw or weight linearity can affect performances (e.g. a classification accuracy) of an analog accelerator (AA) constructed with the Syn-TFTs, the AA simulation is performed to check this with a crossbar simulator. [ABSTRACT FROM AUTHOR]

Gallium nitride high electron mobility transistor (GaN HEMT) devices have become critical components in the manufacturing of high-performance radio frequency (RF) or power electronic modules due to their superior characteristics, such as high electron saturation speeds and high power densities. However, the high heat characteristics of GaN HEMTs make device level cooling a critical problem to solve since performance degradation or even failure may occur under high temperatures. In this paper, we proposed a 2.5D integration method with device-level microchannel direct cooling for a high-power GaN HEMT device. To demonstrate this technological concept, a multigate GaN HEMT device featuring a gate length/width/source drain spacing of 0.5 μm/300 μm/6 μm that underwent in-house backside thinning and metallization was used as the test vehicle. A high-resistivity silicon (HR Si) interposer embedded with four-layer microchannels was designed, having widths/pitches of 30 μm/30 μm at the top microchannel. The high-power GaN HEMT device was soldered on a Si interposer embedded with open microchannels for heat dissipation. A pair of GSG Pad chips was soldered simultaneously to display the capacity for the heterogeneous integration of other chip types. Thermal property evaluation was conducted with experiments and simulations. The test results showed that the maximum surface temperature of the GaN HEMT device decreased to 93.8 °C when it experienced a heat dissipation density of 32 kW/cm2 in the gate finger area and an average heat dissipation density of 5 kW/cm2 was found in the active area with the DI water coolant at a flow rate of 3 mL/min. To our knowledge, among recently reported works, this finding was the best cooling capacity of heterogeneously integrated microchannels for GaN HEMT devices. In addition, this technology was scalable regarding the numbers of gate fingers or GaN HEMT devices. [ABSTRACT FROM AUTHOR]

This work proposes a gas sensor device structure based on conducting polymer (CP) gate and magnesium silicide source heterojunction FET (MSH-DG-TFET) to sense gases such as hexane, methanol, isopropanol, dichloromethane and chloroform. Source material engineering is implemented in the proposed device MSH-DG-TFET to attain higher ON state current at low threshold voltage with reduced subthreshold swing. The working principle of this sensor is the modulation of work function of the sensing element on exposure to gas vapors. With this effect in place, proposed sensor has been investigated for sensitivity against drain current variations and stability over a broad temperature range of 200–400 K for all the gases. Impact of the gate oxide thickness from 2 to 4 nm owing to NONLOCAL intraband tunneling rate on the transfer characteristics of the device has also been investigated in detail. Results reveal that the proposed MSH-DG-TFET gas sensor can be used for analyte gas detection with high sensitivity and reliability in most of the pharmaceutical and chemical industries, where these gases are frequently used. [ABSTRACT FROM AUTHOR]

In this paper, a compact model is presented for the calculation of thermal resistance of gallium oxide-based field-effect transistors (FETs). A gallium oxide epilayer with different substrates of gallium oxide, silicon carbide (SiC), silicon and sapphire is considered for the modeling. Thermal resistance is realized with different epilayer, substrate and gate width thickness. The model is compared and verified on the COMSOL simulation platform with different parametric variations. The model compares favorably with simulation counterparts, with very close agreement (2–3%). Furthermore, channel temperature is also calculated using analytical modeling which helps power device engineers to design the product accordingly. The paper also presents a comparative analysis of the gallium oxide epilayer with different substrates (sapphire, silicon, siC and gallium oxide) to reduce the self-heating effects, which will improve device performance. The gallium oxide epilayer with a SiC substrate-based device shows the best performance in terms of lower thermal resistance and channel temperature. This may help to explore a wide array of possibilities for reducing problems with the thermal characteristics of gallium oxide devices. The analytical modeling presented here helps elucidate the thermal properties of gallium oxide-based devices from both a simulation and fabrication point of view. [ABSTRACT FROM AUTHOR]

We describe an indium bump process applicable to our low-temperature detectors and associated readout. A titanium nitride under bump metallization layer is reactively sputtered onto wiring pads as a diffusion barrier and adhesion layer. Indium is thermally evaporated onto this layer at the desired thickness for bump bonding. Patterning for both titanium nitride and indium layers is accomplished by liftoff techniques. The process flow is compatible with many processes utilized for the fabrication of low-temperature detectors and other superconductive devices. [ABSTRACT FROM AUTHOR]

Nanoporous patterning of two-dimensional materials using block copolymer lithography has drawn much attention. Lateral edge exposures made by the nanoporous patterning provide electrical and optical characteristics that are different from the original materials. However, nanopatterning processes inevitably generate edge exposure and surface defects that may result in poor reliability and reproducibility of the devices. In this study, we propose a reliable method to passivate nanoporous molybdenum disulfide (MoS2) thin-film transistors (TFTs) using polymer thin films, synthesized by initiated chemical vapor deposition (iCVD) to improve the electrical stability of nanoporous MoS2 TFTs. To this end, functional polymer films of electron-donating poly(1-vinylimidzole) (pVI) and inert poly(1H,1H,2H,2H-perfluorodecyl methacrylate) (pPFDMA) were utilized as passivation layers on nanoporous MoS2 TFTs. An n-type doping effect was observed in the pVI-deposited nanoporous MoS2 film due to the electron-donating imidazole ring, whereas the inert pPFDMA efficiently stabilized the electrical characteristics of the nanoporous MoS2 TFTs. Moreover, the hydrophobic fluoroalkyl chain of the pPFDMA film efficiently prevented oxygen and moisture adsorption on the nanoporous MoS2. The superior passivation effect of the pPFDMA layer was confirmed using gate-bias stress tests and long-term storage tests under ambient conditions. [ABSTRACT FROM AUTHOR]

Low-dimensional transition metal dichalcogenides (TMDs) represented by MoS2 have attracted attraction due to their unique structural, physical, and chemical properties. In this work, one-dimensional (1D) MoS2 nanobelts were firstly synthesized on SiO2/Si substrate via chemical vapor deposition (CVD) method. The base planes of MoS2 nanobelt vertically stand on the substrate, which makes the layer edges form the top surface of the nanobelt. By using the micro- and nanoscale fabrication processing, we fabricated field-effect transistor (FET) based on MoS2 nanobelt. The transfer characteristics of the top-gated device indicates that gate modulation in the MoS2 edges is negligible, and the MoS2 edges are found to be a hole metal with the mobility of ~ 0.0023 m2/V·s. The device with zero gate voltage exhibits the carrier concentration of ~ 3.20 × 1013 cm− 2 and resistivity of ~ 8.59 × 104 Ω. The results firstly demonstrate the intrinsic transport properties of metallic edge states in MoS2 nanobelts, which might facilitate the application of MoS2 metallic edges in other aspects in the future. [ABSTRACT FROM AUTHOR]