Search

Code search problems refer to searching a particular bit pattern that satisfies given constraints. Obtaining such codes is very important in fields such as data encoding, error correcting, cryptography, etc. Unfortunately, the search time increases exponentially with the number of bits in the code, and typically requires many months of computation to find large codes. On the other hand, the search method mostly consists of 1-bit computations, so that reconfigurable hardware such as FPGAs (field programmable gate arrays) can be used to successfully obtain a massive degree of parallelism. In this paper, we propose a heterogeneous system with a CPU and an FPGA to speed-up code search problems. According to the evaluation, we obtain over 86 times speed-up compared to typical CPU-based implementation for extremal doubly even self-dual code search problem of length 128.

When designing an FPGA accelerator, efficient memory access is extremely important to obtain high performance. The OpenCL for FPGA uses a hierarchical memory structure that contains memories with different capacities, bandwidths and latencies. Therefore, using those different memories efficiently is very challenging. This chapter explains the problems of memory access and their solutions.

OpenCL-based FPGA design involves several tasks such as emulation, profiling, debugging and optimization. This chapter discusses the design process in detail. It also describes how to interpret various reports generated at different stages of the design process, and how to utilize them for debugging and performance optimization.

In this chapter, we discuss what is an FPGA, and how to design an FPGA-based computing systems using OpenCL. We explain how to setup the OpenCL design environment in step-by-step. An example of an OpenCL design is explained by using a host and a device code. At the end of this chapter, we compare the OpenCL-based design environment against the traditional HDL-based design environment, and discuss the advantages and disadvantages.

OpenCL for FPGA uses two types of kernels: NDRange kernel and single-work-item kernel. This chapter describes how to implement parallel computation using these types of kernel and many optimization strategies for each kernel type.

Recently, C-based OpenCL design environment is proposed to design FPGA (field programmable gate array) accelerators. Although many c-programs can be executed on FPGAs, the best c-code for a CPU may not be the most appropriate one for an FPGA. Users must have some knowledge about computer architecture in order to write a good OpenCL code. In addition, OpenCL-based design process requires several hours of compilation time, because re-writing and compiling many different OpenCL codes may require a very large design time. To solve this problem, we propose an automatic optimization method. We accurately predict the kernel performance using the log files generated at the initial stage of the compilation. Then we find the optimized FPGA architecture by searching all possible design parameters. We implement the proposed method to find the optimized architecture for stencil computation. According to the results, the design time has been reduced to 6–11% of the conventional approach.