Automatic Optimization of OpenCL-Based Stencil Codes for FPGAs

Recently, C-based OpenCL design environment is proposed to design FPGA (field programmable gate array) accelerators. Although many c-programs can be executed on FPGAs, the best c-code for a CPU may not be the most appropriate one for an FPGA. Users must have some knowledge about computer architecture in order to write a good OpenCL code. In addition, OpenCL-based design process requires several hours of compilation time, because re-writing and compiling many different OpenCL codes may require a very large design time. To solve this problem, we propose an automatic optimization method. We accurately predict the kernel performance using the log files generated at the initial stage of the compilation. Then we find the optimized FPGA architecture by searching all possible design parameters. We implement the proposed method to find the optimized architecture for stencil computation. According to the results, the design time has been reduced to 6–11% of the conventional approach.